Datasheet
14
LTC2404/LTC2408
Channel Selection
Typically, CSADC and CSMUX are tied together or CSADC
is inverted and drives CSMUX. SCK and CLK are tied
together and driven with a common clock signal. During
channel selection, CSMUX is HIGH. Data is shifted into the
D
IN
pin on the rising edge of CLK, see Figure 3. Table 3
shows the bit combinations for channel selection. In order
to enable the multiplexer output, CSMUX must be pulled
LOW. The multiplexer should be programmed after the
previous conversion is complete. In order to guarantee the
conversion is complete, the multiplexer addressing should
be delayed a minimum t
CONV
(approximately 133ms for a
60Hz notch) after the data out is read.
While the multiplexer is being programmed, the ADC is in
a low power sleep state. Once the MUX addressing is
complete, the data from the preceding conversion can be
read. A new conversion cycle is initiated following the data
read cycle with the analog input tied to the newly selected
channel.
APPLICATIONS INFORMATION
WUU
U
Table 2. LTC2404/LTC2408 Output Data Format
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 … Bit 4 Bit 3-0
Input Voltage EOC DMY SIG EXR MSB LSB SUB LSBs*
V
IN
> 9/8 • V
REF
001100011...1X
9/8 • V
REF
001100011...1X
V
REF
+ 1LSB 0 0 1 1 0 0 0 0 0 ... 0 X
V
REF
001011111...1X
3/4V
REF
+ 1LSB 0 0 1 0 1 1 0 0 0 ... 0 X
3/4V
REF
001010111...1X
1/2V
REF
+ 1LSB 0 0 1 0 1 0 0 0 0 ... 0 X
1/2V
REF
001001111...1X
1/4V
REF
+ 1LSB 0 0 1 0 0 1 0 0 0 ... 0 X
1/4V
REF
001000111...1X
0
+
/0
–
0 0 1/0** 0 0 0 0 0 0 ... 0 X
–1LSB 0 0 0111 1 11...1 X
–1/8 • V
REF
000111100...0X
V
IN
< –1/8 • V
REF
000111100...0X
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
**The sign bit changes state during the 0 code.
Table 3. Logic Table for Channel Selection
CHANNEL STATUS EN D2 D1 D0
All Off 0 X X X
CH0 1000
CH1 1001
CH2 1010
CH3 1011
CH4* 1100
CH5* 1101
CH6* 1110
CH7* 1111
*Not used for the LTC2404.
Frequency Rejection Selection (F
O
Pin Connection)
The LTC2404/LTC2408 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz ±2% or 60Hz ±2%. For
60Hz rejection, F
O
(Pin 26) should be connected to GND
(Pin 1) while for 50Hz rejection the F
O
pin should be
connected to V
CC
(Pin␣ 2).