LTC2404/LTC2408 4-/8-Channel 24-Bit µPower No Latency ∆ΣTM ADCs U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®2404/LTC2408 are 4-/8-channel 2.7V to 5.5V micropower 24-bit A/D converters with an integrated oscillator, 4ppm INL and 0.3ppm RMS noise. They use delta-sigma technology and provide single cycle digital filter settling time (no latency delay) for multiplexed applications. The first conversion after the channel is changed is always valid.
LTC2404/LTC2408 W W U W ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2404C/LTC2408C .............................. 0°C to 70°C LTC2404I/LTC2408I ...........................
LTC2404/LTC2408 U CONVERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) CONDITIONS Normal Mode Rejection 50Hz ±2% (Note 8) MIN TYP 110 130 dB Power Supply Rejection DC VREF = 2.5V, VIN = 0V 100 dB Power Supply Rejection 60Hz ±2% VREF = 2.5V, VIN = 0V, (Note 7) 110 dB Power Supply Rejection 50Hz ±2% VREF = 2.
LTC2404/LTC2408 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage CS, FO 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 3.3V ● VIL Low Level Input Voltage CS, FO 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V ● VIH High Level Input Voltage SCK 2.7V ≤ VCC ≤ 5.5V (Note 9) 2.7V ≤ VCC ≤ 3.3V (Note 9) ● VIL Low Level Input Voltage SCK 4.
LTC2404/LTC2408 WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER MAX UNITS fEOSC External Oscillator Frequency Range CONDITIONS ● 2.56 MIN 307.2 kHz tHEO External Oscillator High Period ● 0.5 390 µs tLEO External Oscillator Low Period 0.
LTC2404/LTC2408 U W TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error (3V Supply) 10 10 VCC = 3V VREF = 3V 10 VCC = 3V VREF = 3V 5 0 TA = –55°C, –45°C, 25°C, 90°C –5 0 –5 –10 0.5 1.0 1.5 2.0 INPUT VOLTAGE (V) 2.5 3.0 TA = – 45°C 0.5 1.0 1.5 2.0 INPUT VOLTAGE (V) 2.5 3.0 TA = – 55°C 0 – 0.05 – 0.10 – 0.15 – 0.20 – 0.25 – 0.
LTC2404/LTC2408 U W TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs Reference Voltage Offset Error vs VCC 10 5 0 1 0 3 4 2 REFERENCE VOLTAGE (V) – 5.0 2.7 5 3.2 3.7 4.2 4.7 VCC = 5V VREF = 5V VIN = – 0.3V TO 5.3V TA = 25°C 0.50 0 1.5 0 – 2.5 Full-Scale Error vs VCC 6 10.0 VCC = 5V VIN = VREF 5 7.5 5.0 2.5 4 3 2 1 – 5.
LTC2404/LTC2408 U W TYPICAL PERFOR A CE CHARACTERISTICS Sleep Current vs Temperature Conversion Current vs Temperature 220 VCC = 5.5V SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 210 VCC = 4.1V 200 190 VCC= 2.7V 180 170 0 25 –20 VCC = 5.5V 20 VCC = 2.7V 15 10 150 –50 –25 75 50 25 TEMPERATURE (°C) 0 100 50 25 75 0 TEMPERATURE (°C) 100 24048 G19 –70 –90 –110 –130 50 250 100 150 200 FREQUENCY AT VCC (Hz) Rejection vs Frequency at VIN VCC = 4.
LTC2404/LTC2408 U W TYPICAL PERFOR A CE CHARACTERISTICS Resolution vs Maximum Output Rate INL vs Maximum Output Rate VCC = 5V VREF = 5V F0 = EXTERNAL (20480 × MAXIMUM OUTPUT RATE) 22 INL (BITS) 20 18 16 TA = 25°C 14 TA = 90°C 24 20 18 VCC = VREF = 3V 14 12 10 10 8 8 5 10 15 20 25 30 35 40 45 50 55 60 MAXIMUM OUTPUT RATE (Hz) 24048 G27 VCC = VREF = 5V 16 12 0 FO = EXTERNAL (20480 × MAXIMUM OUTPUT RATE) TA = 25°C TA = 90°C 22 RESOLUTION (BITS)* 24 *RESOLUTION = 0 LOG(VREF/RMS NOISE) LO
LTC2404/LTC2408 U U U PIN FUNCTIONS state aborts the data transfer and starts a new conversion. For normal operation, drive this pin in parallel with CSMUX. SDO (Pin 24): Three-State Digital Output. During the data output period this pin is used for serial data output. When the chip select CSADC is high (CSADC = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin can be used as a conversion status output.
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION Converter Operation Cycle CONVERT The LTC2404/LTC2408 are low power, 4-/8-channel deltasigma analog-to-digital converters with easy-to-use 4-wire interfaces. Their operation is simple and made up of four states. The converter operation begins with the conversion, followed by a low power sleep state and concluded with the data output (see Figure 1).
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION Ease of Use The LTC2404/LTC2408 data output has no latency, filter settling or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing an analog input voltage is easy. The LTC2404/LTC2408 perform offset and full-scale calibrations every conversion cycle.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CSADC pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION Table 3. Logic Table for Channel Selection Channel Selection Typically, CSADC and CSMUX are tied together or CSADC is inverted and drives CSMUX. SCK and CLK are tied together and driven with a common clock signal. During channel selection, CSMUX is HIGH. Data is shifted into the DIN pin on the rising edge of CLK, see Figure 3. Table 3 shows the bit combinations for channel selection. In order to enable the multiplexer output, CSMUX must be pulled LOW.
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION –60 The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level. A selection change during the sleep or data output states will not disturb the converter operation. If the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION Using an External Clock for Faster Conversion Times The conversion time of the LTC2404/LTC2408 is determined by the conditions on the FO pin. If FO is connected to GND for 60Hz rejection, the conversion time is 133µs. If FO is connected to VCC, the conversion time is 160µs.
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION is used as an end of conversion indicator during the conversion and sleep states. When CSADC (Pin 23) is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CSADC is LOW during the convert or sleep state, SDO will output EOC. If CSADC is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION 2.7V TO 5.5V VCC VCC = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION FO LTC2404/LTC2408 0.1V TO VCC –0.12VREF TO 1.12VREF VREF CSMUX CH0 TO CH7 CSADC MUXOUT ADCIN GND SCK CS SCK CLK DIN SDO CSADC/ CSMUX SCK/CLK TEST EOC BIT31 TEST EOC BIT30 BIT29 BIT28 BIT27 BIT26 SDO SIG Hi-Z DIN DON’T CARE EXR MSB Hi-Z EN D2 D1 D0 BIT4 BIT0 LSB SUB LSB TEST EOC Hi-Z DON’T CARE 24048 F07 Figure 7.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION CSADC/ CSMUX SCK/CLK TEST EOC BIT31 BIT30 TEST EOC BIT29 BIT28 BIT27 BIT26 SDO SIG EXR MSB BIT4 BIT0 LSB SUB LSB Hi-Z DIN CONVERTER STATE DON’T CARE CONV SLEEP EN DATA OUTPUT D2 D1 D0 DON’T CARE INTERNAL CALIBRATION CONVERSION ON SELECTED CHANNEL 66ms CONVERT 66ms LOOK AHEAD 133ms CONVERSION CYCLE (OUTPUT RATE = 7.5Hz) 24048 F08 Figure 8. Use of Look Ahead to Program Multiplexer After Data Output 2.7V TO 5.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION 2.7V TO 5.5V VCC VCC = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION FO LTC2404/LTC2408 0.1V TO VCC –0.12VREF TO 1.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH, and a new conversion starts. Typically, CSADC remains LOW during the data output state.
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2404/LTC2408’s internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CSADC, the device is switched to the external SCK timing mode. By adding an external 10k pullup resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION power dissipation. A series resistor between 27Ω and 56Ω placed near the driver or near the LTC2404/LTC2408 pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology. performance of the device. It simply results in an offset/ full-scale shift, see Figure 13.
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION 300 50 OFFSET ERROR (ppm) 40 30 OFFSET ERROR (ppm) VCC = 5V VREF = 5V VIN = 0V TA = 25°C CIN = 0pF CIN = 100pF CIN = 1000pF 20 CIN = 0.01µF 10 0 CIN = 1µF CIN = 10µF VCC = 5V VREF = 5V 250 VIN = 0V TA = 25°C 200 CIN = 0.1µF 150 100 CIN = 0.01µF 50 0 1 10 1k 100 RSOURCE (Ω) 10k 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω) 100k 24048 F17 Figure 15. Offset vs RSOURCE (Small C) Figure 17.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION Reference Current (VREF) Similar to the analog input, the reference input has a dynamic input current. This current has negligible effect on the offset. However, the reference current at VIN = VREF is similar to the input current at full-scale. For large values of reference capacitance (CVREF > 0.01µF), the full-scale error shift is 0.3ppm/Ω of external reference resistance independent of the capacitance at VREF, see Figure 19.
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION ANTIALIASING One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2404/LTC2408 significantly simplify antialiasing filter requirements. The digital filter provides very high rejection except at integer multiples of the modulator sampling frequency (fS), see Figure 23.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION 5V 300µA + R2 6 47µF 5V LTC1634-2.5 3 4 5 + 7 6 LTC1050 2 R1 20.1k 0.1% UP TO SEVERAL HUNDRED FEET. ALL SAME WIRE TYPE PT1 100Ω PLATINUM RTD PT7 R2 5V OPTIONAL PROTECTION RESISTORS 5k MAX 7 MUXOUT 4 ADCIN 3 2, 8 VREF VCC 1µF 9 CH0 10 CH1 CSADC 11 CH2 CSMUX 13 CH4 TO PT3-PT6 4 R3 12 CH3 PT2 – 0.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION 5V VIN 3 AV = 1, 2, 4...128 + 6 LTC1050 2 – 5V 0.1V TO VCC 10k 20k 7 MUXOUT 2 10k 4 20k 20k 10k 8 10k 16 20k 10k 20k 10k 32 10k 20k 10k 1µF 9 CH0 10 CH1 CSADC 11 CH2 CSMUX 12 CH3 13 CH4 14 CH5 DIN 15 CH6 SDO 17 CH7 SCK 24-BIT ∆Σ ADC 8-CHANNEL MUX CLK 23 20 25 19 21 24 VCC LTC2408 64 20k 3 2, 8 VREF VCC 4 ADCIN FO GND 1, 5, 6, 16, 18, 22, 27, 28 26 2404/08 F25 128 Figure 25.
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION noise bandwidth of the system to 6Hz. The noise bandwidth of the LTC2408 without any input bandwidth limiting is approximately 150Hz. A roll-off at 1500Hz eliminates all higher order images of the base bandwidth of 6Hz. In the example shown, the optional bandwidthlimiting filter has a – 3dB point at 1450Hz.
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION DIN1 EQU $00 This memory location holds the LTC2408’s bits 31 - 24 DIN2 EQU $01 This memory location holds the LTC2408’s bits 23 - 16 DIN3 EQU $02 This memory location holds the LTC2408’s bits 15 - 08 DIN4 EQU $03 This memory location holds the LTC2408’s bits 07 - 00 MUX EQU $04 This memory location holds the MUX address data * *************************************** * Start GETDATA Routine * *************************************** * ORG $C000 Program sta
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION * *************************************** * The SPI data transfer * *************************************** * TRFLP1 LDAA #$0 Load accumulator A with a null byte for SPI transfer STAA SPDR This writes the byte into the SPI data register and * starts the transfer WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial * transfer/exchange by reading the SPI Status Register BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR’s * MSB and
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION ***************************************************************************** * * * This example program loads multiplexer channels selection data into * * either the LTC2408’s internal MUX or an external LTC1391 MUX. It then * * transfers the LTC2408’s 32-bit output conversion result to four * * consecutive 8-bit memory locations.
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION ENLWMX TBA ORAA MUXSPI STAA * WAITMUX LDAA #$08 SPDR SPSR BPL Restore contents of Accum. A Set the MUX’s ENABLE bit Transfer Accum.
LTC2404/LTC2408 U W U U APPLICATIONS INFORMATION amplifier-based or self-contained instrumentation amplifiers (also available from LTC) can be used with the LTC2408. With the resistor network connected to CH0, the LTC2408 is able to measure DC voltages from 1mV to 1kV in a single range without the need for autoranging. The 990k resistor should be a 1W resistor rated for high voltage operation.
LTC2404/LTC2408 U U W U APPLICATIONS INFORMATION These infrared thermocouples are self-contained: 1) they do not require external cold junction compensation; 2) they cannot use conventional open thermocouple detection schemes; and 3) their output impedances are high, approximately 3kΩ.
LTC2404/LTC2408 U TYPICAL APPLICATION GUARD RING 5V ELECTROMETER INPUT (pH, PIEZO) 3 7 + 2 R5 5k, 1% 6 LT1793 DC VOLTMETER INPUT 1mV TO 1000V R1 900k 0.1%, 1W, 1000 WVDC R2 4.7k 0.1% – 0V TO 5V 4 –5V 5V REF + R4 1k –60mV TO 4V R3, 10k C1, 0.1µF 5V MAX LT1236CS8-5 6 2 OUT IN + GND 4 10µF 3-WIRE R-PACK 60Hz + AC INPUT R6 10k, 0.1% 100µF R7 10k, 0.1% 5V 5V 1µF 2 RT 7 – IN914 3 R9 1k 1% IN914 R10 5k 1% 6 LTC1050 7 MUXOUT 11 CH2 12 CH3 13 CH4 R11 24.9k, 0.
