Datasheet

23
LTC2401/LTC2402
reference, on a regular FR-4 board, signal propagation
velocity is approximately 183ps/inch for internal traces
and 170ps/inch for surface traces. Thus, a driver gener-
ating a control signal with a minimum transition time of
1ns must be connected to the converter pin through a
trace shorter than 2.5 inches. This problem becomes
particularly difficult when shared control lines are used
and multiple reflections may occur. The solution is to
carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2401/LTC2402 pin will
eliminate this problem but will increase the driver power
dissipation. A series resistor between 27Ω and 56Ω
placed near the driver or near the LTC2401/LTC2402 pin
will also eliminate this problem without additional power
dissipation. The actual resistor value depends upon the
trace impedance and connection topology.
Driving the Input and Reference
The analog input and reference of the typical delta-sigma
analog-to-digital converter are applied to a switched ca-
pacitor network. This network consists of capacitors
switching between the analog input (V
IN
), ZS
SET
(Pin 5)
and FS
SET
(Pin 2). The result is small current spikes seen
at both V
IN
and V
REF
. A simplified input equivalent circuit
is shown in Figure 15.
The key to understanding the effects of this dynamic
input current is based on a simple first order RC time
constant model. Using the internal oscillator, the
LTC2401/LTC2402’s internal switched capacitor network
is clocked at 153,600Hz corresponding to a 6.5µs sam-
pling period. Fourteen time constants are required each
time a capacitor is switched in order to achieve 1ppm
settling accuracy.
Therefore, the equivalent time constant at V
IN
and V
REF
should be less than 6.5µs/14 = 460ns in order to achieve
1ppm accuracy.
Input Current (V
IN
)
If complete settling occurs on the input, conversion results
will be uneffected by the dynamic input current. If the
settling is incomplete, it does not degrade the linearity
performance of the device. It simply results in an offset/
full-scale shift, see Figure 16. To simplify the analysis of
input dynamic current, two separate cases are assumed:
large capacitance at V
IN
(C
IN
> 0.01µF) and small capaci-
tance at V
IN
(C
IN
< 0.01µF).
APPLICATIO S I FOR ATIO
WUUU
FS
SET
CH0/CH1
V
CC
R
SW
5k
AVERAGE INPUT CURRENT:
I
IN
= 0.25(V
IN
– 0.5 • V
REF
)fC
EQ
I
REF(LEAK)
I
REF(LEAK)
V
CC
R
SW
5k
C
EQ
2.5pF (TYP)
R
SW
5k
I
IN(LEAK)
I
IN
24012 F15
I
IN(LEAK)
SWITCHING FREQUENCY
f = 153.6kHz FOR INTERNAL OSCILLATOR (f
O
= LOGIC LOW OR HIGH)
f = f
EOSC
FOR EXTERNAL OSCILLATORS
ZS
SET
Figure 15. LTC2401/LTC2402 Equivalent Analog Input Circuit
ZS
SET
TUE
V
IN
24012 F16
FS
SET
Figure 16. Offset/Full-Scale Shift
If the total capacitance at V
IN
(see Figure 17) is small
(<0.01µF), relatively large external source resistances (up
to 20k for 20pF parasitic capacitance) can be tolerated
without any offset/full-scale error. Figures 18 and 19 show
a family of offset and full-scale error curves for various
small valued input capacitors (C
IN
< 0.01µF) as a function
of input source resistance.
For large input capacitor values (C
IN
> 0.01µF), the input
spikes are averaged by the capacitor into a DC current. The
gain shift becomes a linear function of input source