Datasheet

16
LTC2401/LTC2402
Figure 5. External Serial Clock, Single Cycle Operation
APPLICATIO S I FOR ATIO
WUUU
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
TEST EOC
MSB SUB LSBEXRCH0/CH1
BIT 0
LSB
BIT 4BIT 27 BIT 26BIT 28BIT 29BIT 30
SLEEP DATA OUTPUT CONVERSION
24012 F05
CONVERSION
Hi-ZHi-ZHi-Z
TEST EOCTEST EOC
V
CC
F
O
FS
SET
ZS
SET
SCK
CH1 SDO
GND
CS
REFERENCE VOLTAGE
ZS
SET
+ 0.1V TO V
CC
0V TO FS
SET
– 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1µF
110
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2402
V
CC
3-WIRE
SERIAL I/O
ANALOG INPUT RANGE
ZS
SET
– 0.12V
REF
TO
FS
SET
+ 0.12V
REF
(V
REF
= FS
SET
– ZS
SET
)
SDO
SCK
(EXTERNAL)
CS
DATA OUTPUT
CONVERSIONSLEEP SLEEP
TEST EOC TEST EOC
DATA OUTPUT
Hi-Z Hi-ZHi-Z
CONVERSION
24012 F06
MSBEXRSIGCH0/CH1
BIT 8BIT 27 BIT 9BIT 28BIT 29BIT 30
EOC
BIT 31BIT 0
EOC
Hi-Z
TEST EOC
V
CC
F
O
FS
SET
ZS
SET
SCK
CH1 SDO
GND
CS
REFERENCE VOLTAGE
ZS
SET
+ 0.1V TO V
CC
0V TO FS
SET
– 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1µF
110
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2402
V
CC
3-WIRE
SERIAL I/O
ANALOG INPUT RANGE
ZS
SET
– 0.12V
REF
TO
FS
SET
+ 0.12V
REF
(V
REF
= FS
SET
– ZS
SET
)
Figure 6. External Serial Clock, Reduced Data Output Length