Datasheet

12
LTC2401/LTC2402
APPLICATIO S I FOR ATIO
WUUU
Figure 3. Output Data Timing
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0␣ ≤␣V
IN
≤ V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2401/LTC2402 Status Bits
Bit 31 Bit 30 Bit 29 Bit 28
Input Range EOC CH0/CH1 SIG EXR
V
IN
> V
REF
0 0/1 1 1
0 < V
IN
≤ V
REF
0 0/1 1 0
V
IN
= 0
+
/0
–
0 0/1 1/0 0
V
IN
< 0 0 0/1 0 1
Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the V
IN
pin is maintained within
the –0.3V to (V
CC
+ 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from –0.125 • V
REF
to 1.125 • V
REF
. For input voltages
greater than 1.125 • V
REF
, the conversion result is clamped
to the value corresponding to 1.125 • V
REF
. For input
voltages below –0.125 • V
REF
, the conversion result is
clamped to the value corresponding to –0.125 • V
REF
.
Frequency Rejection Selection (F
O
Pin Connection)
The LTC2401/LTC2402 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz ±2% or 60Hz ±2%. For
60Hz rejection, F
O
(Pin 10) should be connected to GND
(Pin 6) while for 50Hz rejection the F
O
pin should be
connected to V
CC
(Pin␣ 1).
The selection of 50Hz or 60Hz rejection can also be made
by driving F
O
to an appropriate logic level. A selection
change during the sleep or data output states will not
MSBEXTSIGCH0/CH1
1 2 3 4 5 272832
BIT 0BIT 27 BIT 4
LSB
24
BIT 28BIT 29BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP DATA OUTPUT CONVERSION
24012 F03
Hi-Z