Datasheet

11
LTC2401/LTC2402
integrity of the conversion result and of the serial interface
mode selection which is performed at the initial power-up.
(See the 2-wire I/O sections in the Serial Interface Timing
Modes section.)
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2401/LTC2402 start a normal conversion
cycle and follows the normal succession of states de-
scribed above. The first conversion result following POR
is accurate within the specifications of the device.
Reference Voltage Range
The LTC2401/LTC2402 can accept a reference voltage
(V
REF
= FS
SET
– ZS
SET
) from 0V to V
CC
. The converter
output noise is determined by the thermal noise of the
front-end circuits, and as such, its value in microvolts is
nearly constant with reference voltage. A decrease in
reference voltage will not significantly improve the
converter’s effective resolution. On the other hand, a
reduced reference voltage will improve the overall con-
verter INL performance. The recommended range for the
LTC2401/LTC2402 voltage reference is 100mV to V
CC
.
Input Voltage Range
The converter is able to accommodate system level
offset and gain errors as well as system level overrange
situations due to its extended input range, see Figure 2.
The LTC2401/LTC2402 convert input signals within the
extended input range of –0.125 • V
REF
to 1.125 • V
REF
(V
REF
= FS
SET
– ZS
SET
).
For large values of V
REF
(V
REF
= FS
SET
– ZS
SET
), this range
is limited by the absolute maximum voltage range of
–0.3V to (V
CC
+ 0.3V). Beyond this range, the input ESD
protection devices begin to turn on and the errors due to
the input leakage current increase rapidly.
Input signals applied to V
IN
may extend below ground by
–300mV and above V
CC
by 300mV. In order to limit any
fault current, a resistor of up to 5k may be added in series
with the V
IN
pin without affecting the performance of the
device. In the physical layout, it is important to maintain
APPLICATIO S I FOR ATIO
WUUU
the parasitic capacitance of the connection between this
series resistance and the V
IN
pin as low as possible;
therefore, the resistor should be located as close as
practical to the V
IN
pin. The effect of the series resistance
on the converter accuracy can be evaluated from the
curves presented in the Analog Input/Reference Current
section. In addition, a series resistor will introduce a
temperature dependent offset error due to the input leak-
age current. A 1nA input leakage current will develop a
1ppm offset error on a 5k resistor if V
REF
= 5V. This error
has a very strong temperature dependency.
Output Data Format
The LTC2401/LTC2402 serial output data stream is 32 bits
long. The first 4 bits represent status information indicat-
ing the sign, selected channel, input range and conversion
state. The next 24 bits are the conversion result, MSB first.
The remaining 4 bits are sub LSBs beyond the 24-bit level
that may be included in averaging or discarded without
loss of resolution.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW when
the conversion is complete.
Bit 30 (second output bit) for the LTC2402, this bit is LOW
if the last conversion was performed on CH0 and HIGH for
CH1. This bit is always low for the LTC2401.
24012 F02
V
CC
+ 0.3V
FS
SET
+ 0.12V
REF
FS
SET
–0.3V
(V
REF
= FS
SET
– ZS
SET
)
ZS
SET
– 0.12V
REF
ZS
SET
NORMAL
INPUT
RANGE
EXTENDED
INPUT
RANGE
ABSOLUTE
MAXIMUM
INPUT
RANGE
Figure 2. LTC2401/LTC2402 Input Range