Datasheet

LTC2389-18
33
238918f
applicaTions inFormaTion
Serial Bus Configuration
In applications where a serial bus is required to minimize
the data bus width, the LTC2389-18 is capable of providing
each conversion result R[17:0] serially on pin D12/SDO.
To select this bus configuration, pins MODE = MODE[1:0]
should be driven to MODE = 11, as described in Table 1. As
shown in Figure 19, the serial output data is presented on the
SDO pin in response to an external shift clock input applied
to the SCK pin. The data on SDO changes state following
rising edges of SCK. The one exception to this behavior
is that D17 remains valid until the first SCK rising edge
following the first SCK falling edge. If CS is used to gate
the serial output data, the full conversion result should be
read before CS is returned to a high level. For best perfor-
mance do not clock serial data out when BUSY is high.
The SDI input pin can be used to daisy chain multiple
converters, as shown in Figure 19. In this figure, two
devices are cascaded with the MSB of ADC1 appearing
at the serial output of ADC2 after an 18 SCK cycle delay.
The serial output of ADC1 is clocked into
ADC2 on the
falling edges of SCK. This is useful in applications where
hardware constraints limit the number of data lines avail-
able to interface with multiple converters.
Data Format
The binary format of the conversion result depends on the
state of pins PD/FD and OB/2C, as described in Table2.
These pins are active in both the parallel and serial modes
of operation.
Reset
As shown in Figure 20, when the RESET pin is high, the
LTC2389-18 is reset and the data bus is put into a high
impedance mode. If this occurs during a conversion, the
conversion is immediately halted. In reset, requests for
new conversions are ignored. Once RESET returns low,
the LTC2389-18 is ready to start a new conversion after
the acquisition time has been met.
Figure 20. RESET Pin Timing
RESET
DATA BUS D[17:0]
Hi-Z
CVNST
t
RESETH
t
ACQ
238918 F20