Datasheet
LTC2389-18
14
238918f
output bus, as described in Table 1. When MODE = 11,
this pin is the serial data output line, which serially outputs
the result of the most recent conversion clocked by SCK.
The data is output MSB first on the rising edge of SCK.
The data format is determined by the logic levels of pins
PD/FD and OB/2C, as described in Table 2. Logic levels
are determined by OV
DD
.
D13/SCK (Pin 24): Data Bit 13/Serial Clock Input. When
MODE = 00, 01 or 10, this pin is Bit 13 of the parallel data
output bus, as described in Table 1. When MODE = 11,
this pin this is the serial clock input. Logic levels are
determined by OV
DD
.
D14 (Pin 25): Data Bit 14. When MODE = 00, 01 or 10, this
pin is Bit 14 of the parallel data output bus, as described
in Table 1. Logic levels are determined by OV
DD
.
D15 (Pin 26): Data Bit 15. When MODE = 00, 01 or 10, this
pin is Bit 15 of the parallel data output bus, as described
in Table 1. Logic levels are determined by OV
DD
.
D16 (Pin 27): Data Bit 16. When MODE = 00, 01 or 10, this
pin is Bit 16 of the parallel data output bus, as described
in Table 1. Logic levels are determined by OV
DD
.
D17 (Pin 28): Data Bit 17. When MODE = 00, 01
or 10, this
pin is Bit 17 of the parallel data output bus, as described
in Table 1. Logic levels are determined by OV
DD
.
BUSY (Pin 29): Busy Output. This pin transitions low to
high at the start of each conversion and stays high until
the conversion is complete. The falling edge of BUSY can
be used as the data-ready clock signal. Logic levels are
determined by OV
DD
.
PD/FD (Pin 30): Pseudo-Differential/ Fully-Differential
Input. This pin, in conjunction with Pin 6 (OB/2C), controls
the analog input range of the converter and the binary
format of the conversion result, as described in Table 2.
Logic levels are determined by OV
DD
.
CS (Pin 31): Chip Select Input. The data I/O bus is enabled
when CS is low and goes Hi-Z when CS is high. CS also
gates the external shift clock. Logic levels are determined
by OV
DD
.
RESET (Pin 32): Reset Input. When this pin is brought high,
the LTC2389-18 is reset. If this occurs during a conver-
sion, the conversion is halted and the data bus becomes
Hi-Z. Logic levels are determined by OV
DD
.
pin FuncTions
Table 1. Data Bus Configuration Table. Use Inputs MODE1 and MODE0 to Select Bus Configuration Based on Application Bus Width.
In 16-Bit and 8-Bit Parallel Configurations, Inputs D1/A1 and D0/A0 Control Mapping of Conversion Result R[17:0] Onto Data Bus
Pins D[17:2]. Shaded Cells Denote Bidirectional Pins Configured as Inputs.
BUS
CONFIGURATION
MODE1 MODE0 D[17:16] D[15:14] D13 D12 D11 D10 D[9:4] D[3:2] D1/A1 D0/A0
18-Bit Parallel 0 0 R[17:0]
16-Bit Parallel 0 1 R[17:2] X 0
All Zeros R[1:0] 0 1
R[1:0] All Zeros 1 1
8-Bit Parallel 1 0 R[17:10] All Hi-Z 0 0
All Zeros R[1:0] All Hi-Z 0 1
R[9:2] All Hi-Z 1 0
R[1:0] All Zeros All Hi-Z 1 1
Serial 1 1 All Hi-Z SCK SDO SDI All Hi-Z