Datasheet

LTC2389-18
13
238918f
pin FuncTions
GND (Pins 1, 17, 20, 35, 41, 44, 48, Exposed Pad
Pin 49 (QFN Only)): Ground. Solder all GND pins and
exposed pad to the ground plane.
V
DD
(Pins 2, 3, 19, 40, 45, 46, 47): 5V Power Supply.
The range of V
DD
is 4.75V to 5.25V. Bypass V
DD
network
to GND with a 0.1μF ceramic capacitor close to each pin
and a 10μF ceramic capacitor in parallel.
MODE0, MODE1 (Pin 4, Pin 5): Data Bus Configuration
Inputs. These pins control the parsing and presentation
of conversion results on the output data bus. Based on
the state of MODE = MODE[1:0], the bus is configured to
provide either 18-bit parallel (MODE = 00), 16-bit paral-
lel (MODE = 01), 8-bit parallel (MODE = 10) or serial
(MODE = 11) data, as described in Table 1. Digital outputs
that are not active in a particular mode become Hi-Z.
Logic levels are determined by OV
DD
. For information
regarding pin compatibility with 16-bit versions of the
LTC238x family, refer to the Pin Compatibility with
LTC238x-16 section.
OB/2C (Pin 6): Offset Binary/ Two’s Complement Input.
This pin, in conjunction with Pin 30 (PD/FD), controls the
analog input range of the converter and the binary format
of the conversion result, as described in Table 2. Logic
levels are determined by
OV
DD
.
D0/A0 (Pin 7): Data Bit 0/Address Bit 0. When MODE = 00,
this pin is Bit 0 of the parallel data output bus. When
MODE = 01 or 10, this pin is Bit 0 of the parallel address
input bus, where the binary address A[1:0] determines
which segment of the conversion result is driven on
the upper bits of the output data bus, as described in
Table1. Logic levels are determined by OV
DD
. For infor-
mation regarding pin compatibility with 16-bit versions
of the LTC238x family, refer to the Pin Compatibility with
LTC238x-16 section.
D1/A1 (Pin 8): Data Bit 1/Address Bit 1. When MODE = 00,
this pin is Bit 1 of the parallel data output bus. When MODE
= 01 or 10, this pin is Bit 1 of the parallel address input
bus, where the binary address A[1:0] determines which
segment of the conversion result is driven on the upper
bits of the output data bus, as described in Table 1. Logic
levels are determined by OV
DD
. For information regarding
pin compatibility with 16-bit versions of the LTC238x family,
refer to the Pin Compatibility with LTC238x-16 section.
D2 (Pin 9): Data Bit 2. When MODE = 00 or 01, this pin
is Bit 2 of the parallel data output bus, as described in
Table1. Logic levels are determined by OV
DD
.
D3 (Pin 10): Data Bit 3. When MODE = 00 or 01, this pin
is Bit 3 of the parallel data output bus, as described in
Table 1. Logic levels are determined by OV
DD
.
D4 (Pin 11): Data Bit 4. When MODE = 00 or 01, this pin
is Bit 4 of the parallel data output bus, as described in
Table 1. Logic levels are determined by OV
DD
.
D5 (Pin 12): Data Bit 5. When MODE = 00 or 01, this pin
is Bit 5 of the parallel data output bus, as described in
Table 1. Logic levels are determined by OV
DD
.
D6 (Pin 13): Data Bit 6. When MODE = 00 or 01, this pin
is Bit 6 of the parallel data output bus, as described in
Table 1. Logic levels are determined by OV
DD
.
D7 (Pin 14): Data Bit 7. When MODE = 00 or 01, this pin
is Bit 7 of the parallel data output bus, as described in
Table 1. Logic levels are determined by OV
DD
.
D8 (Pin 15): Data Bit 8. When MODE = 00 or 01, this pin
is Bit 8 of the parallel data output bus, as described in
Table 1. Logic levels are determined by OV
DD
.
D9 (Pin 16): Data Bit 9. When MODE = 00 or 01, this pin
is Bit 9 of the parallel data output bus, as described in
Table 1. Logic
levels are determined by OV
DD
.
OV
DD
(Pin 18): I/O Interface Power Supply. The range of
OV
DD
is 1.71V to 5.25V. Bypass OV
DD
to GND close to the
pin with a 0.1μF and a 10μF ceramic capacitor in parallel.
D10 (Pin 21): Data Bit 10. When MODE = 00, 01 or 10, this
pin is Bit 10 of the parallel data output bus, as described
in Table 1. Logic levels are determined by OV
DD
.
D11/SDI (Pin 22): Data Bit 11/Serial Data Input. When
MODE = 00, 01 or 10, this pin is Bit 11 of the parallel data
output bus, as described in Table 1. When MODE = 11,
this pin is the serial data input, which can be used to daisy
chain two or more converters on a single SDO line. The
digital data level on SDI is output on SDO with a delay of
18 SCK periods after the start of the read sequence. Logic
levels are determined by OV
DD
.
D12/SDO (Pin 23): Data Bit 12/Serial Data Output. When
MODE = 00, 01 or 10, this pin is Bit 12 of the parallel data