LTC2389-18 18-Bit, 2.5Msps SAR ADC with Pin-Configurable Analog Input Range and 99.8dB SNR Description Features n n n n n n n n n n n n n n n 2.5Msps Throughput Rate ±3LSB INL (Max) Guaranteed 18-Bit, No Missing Codes Pin-Configurable Analog Input Range: ±4.096V Fully Differential 0V to 4.096V Pseudo-Differential Unipolar ±2.048V Pseudo-Differential Bipolar 99.8dB (Fully Differential)/95.
LTC2389-18 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage (VDD , OVDD)........................................6V Analog Input Voltage (Note 3) IN+, IN–, REFIN, CNVST......(GND – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V) Digital Output Voltage (Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V) Power Dissipation............................................... 500mW Operating Temperature Range LTC2389C.....................
LTC2389-18 Analog Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN+ Absolute Input Range (IN+) MIN TYP (Note 5) l –0.1 VREF + 0.1 V VIN– Absolute Input Range (IN–) Fully Differential (Note 5) Pseudo-Differential Unipolar (Note 5) Pseudo-Differential Bipolar (Note 5) l l l –0.1 –0.1 VREF /2 – 0.1 VREF + 0.1 0.1 VREF /2 + 0.
LTC2389-18 Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS (Notes 4, 8) SYMBOL PARAMETER CONDITIONS SINAD Signal-to-(Noise + Distortion) Ratio Fully Differential, fIN = 2kHz Pseudo-Differential Unipolar, fIN = 2kHz Pseudo-Differential Bipolar, fIN = 2kHz SNR THD SFDR MIN TYP l l l 97.3 92.2 92.7 99.7 94.5 95.
LTC2389-18 Digital Inputs And Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC2389-18 Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC2389-18 Typical Performance Characteristics TA = 25°C, VDD = 5V, OVDD = 2.5V, VREF = 4.096V External Reference, Fully Differential Range (PD/FD = 0V), VCM = 2.048V, fSMPL = 2.5Msps, unless otherwise noted. Differential Nonlinearity vs Output Code 1.0 INTERNAL REF EXTERNAL REF 1.5 0 –0.5 0.4 80000 0.2 COUNTS DNL ERROR (LSB) 0 –0.2 40000 –0.4 –0.6 –1.5 20000 –0.8 0 65536 131072 196608 OUTPUT CODE –1.0 262144 0 65536 131072 196608 OUTPUT CODE 238918 G01 0 262144 120000 4.
LTC2389-18 Typical Performance Characteristics TA = 25°C, VDD = 5V, OVDD = 2.5V, VREF = 4.096V External Reference, Fully Differential Range (PD/FD = 0V), VCM = 2.048V, fSMPL = 2.5Msps, unless otherwise noted. THD, Harmonics vs Temperature, fIN = 2kHz SNR, SINAD vs Temperature, fIN = 2kHz 102 –110 2 –115 SNR 100 SINAD 99 98 THD 3RD –120 –125 2ND –130 97 96 –55 –35 –15 –135 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 238918 G10 Offset Error vs Temperature 0 –0.5 –1.
LTC2389-18 Typical Performance Characteristics TA = 25°C, VDD = 5V, OVDD = 2.5V, VREF = 4.096V External Reference, Pseudo-Differential Unipolar Range (PD/FD = OVDD, OB/2C = OVDD), fSMPL = 2.5Msps, unless otherwise noted. Differential Nonlinearity vs Output Code Integral Nonlinearity vs Output Code 2.0 1.0 INTERNAL REF EXTERNAL REF 1.5 0.6 0 –0.5 60000 0.4 0.2 COUNTS DNL ERROR (LSB) 0 –0.2 –0.4 20000 –0.6 –1.5 40000 –0.8 0 65536 131072 196608 –1.
LTC2389-18 Typical Performance Characteristics TA = 25°C, VDD = 5V, OVDD = 2.5V, VREF = 4.096V External Reference, Pseudo-Differential Unipolar Range (PD/FD = OVDD, OB/2C = OVDD), fSMPL = 2.5Msps, unless otherwise noted. Offset Error vs Temperature 2.0 THD –115 1.5 2ND –120 3RD –125 MAX INL 1 OFFSET ERROR (LSB) –110 THD, HARMONICS (dB) INL/DNL vs Temperature 2 INL/ DNL ERROR (LSB) –105 THD, Harmonics vs Temperature, fIN = 2kHz MAX DNL 0 MIN DNL MIN INL –1 –130 –135 –55 –35 –15 1.0 0.
LTC2389-18 Typical Performance Characteristics TA = 25°C, VDD = 5V, OVDD = 2.5V, VREF = 4.096V External Reference, Pseudo-Differential Bipolar Range (PD/FD = OVDD, OB/2C = OV), fSMPL = 2.5Msps, unless otherwise noted. Differential Nonlinearity vs Output Code 1.0 INTERNAL REF EXTERNAL REF 1.5 0.6 0 –0.5 –1.0 0.2 0 –0.2 –0.4 –0.8 0 65536 131072 196608 OUTPUT CODE –1.0 262144 0 65536 131072 196608 0 262144 OUTPUT CODE 238918 G33 238918 G34 32k Point FFT fSMPL = 2.
LTC2389-18 Typical Performance Characteristics TA = 25°C, VDD = 5V, OVDD = 2.5V, VREF = 4.096V External Reference, Pseudo-Differential Bipolar Range (PD/FD = OVDD, OB/2C = OV), fSMPL = 2.5Msps, unless otherwise noted. 2ND –125 –130 MAX INL 1 OFFSET ERROR (LSB) THD, HARMONICS (dB) 1.5 –120 –135 –55 –35 –15 Offset Error vs Temperature 2.0 THD –110 –115 INL/DNL vs Temperature 2 INL/ DNL ERROR (LSB) –105 THD, Harmonics vs Temperature, fIN = 2kHz MAX DNL 0 MIN DNL MIN INL –1 1.0 0.5 0 –0.
LTC2389-18 Pin Functions GND (Pins 1, 17, 20, 35, 41, 44, 48, Exposed Pad Pin 49 (QFN Only)): Ground. Solder all GND pins and exposed pad to the ground plane. D2 (Pin 9): Data Bit 2. When MODE = 00 or 01, this pin is Bit 2 of the parallel data output bus, as described in Table 1. Logic levels are determined by OVDD. VDD (Pins 2, 3, 19, 40, 45, 46, 47): 5V Power Supply. The range of VDD is 4.75V to 5.25V. Bypass VDD network to GND with a 0.
LTC2389-18 Pin Functions D17 (Pin 28): Data Bit 17. When MODE = 00, 01 or 10, this pin is Bit 17 of the parallel data output bus, as described in Table 1. Logic levels are determined by OVDD. output bus, as described in Table 1. When MODE = 11, this pin is the serial data output line, which serially outputs the result of the most recent conversion clocked by SCK. The data is output MSB first on the rising edge of SCK.
LTC2389-18 Pin Functions PD (Pin 33): Power-Down Input. When this pin is brought high, the LTC2389-18 is powered down and subsequent conversion requests are ignored. Before enabling powerdown, the result of the last conversion result should be read. Logic levels are determined by OVDD. CNVST (Pin 34): Conversion Start Input. A falling edge on this pin puts the internal sample-and-hold into the hold mode and starts a conversion. CNVST is independent of CS. Logic levels are determined by VDD.
LTC2389-18 FUNCTIONAL Block Diagram VDD OVDD LTC2389-18 18-BIT, 16-BIT OR 8-BIT BUS SDI SDO IN+ 18-BIT SAMPLING ADC IN– 18 BITS PARALLEL/ SERIAL INTERFACE SCK CS MODE1 1x BUFFER MODE0 REFIN A1 A0 REFOUT VCM 4.
LTC2389-18 Timing Diagrams Conversion Timing Using the Parallel Interface CS = RESET = 0 CNVST CONVERT BUSY D[17:0] ACQUIRE PREVIOUS CONVERSION CURRENT CONVERSION Conversion Timing Using the Serial Interface CS = RESET = 0 CNVST BUSY CONVERT SCK SDO ACQUIRE 1 DON’T CARE 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 238918 TD01 238918f 17
LTC2389-18 Applications Information TRANSFER FUNCTION The LTC2389-18 is a low noise, high speed 18-bit successive approximation register (SAR) ADC. Operating from a single 5V supply, the LTC2389-18 supports pin-configurable fully differential (±4.096V), pseudo-differential unipolar (0V to 4.096V) and pseudo-differential bipolar (±2.048V) analog input ranges, allowing it to interface with multiple signal chain formats without requiring additional level translation or signal conditioning.
LTC2389-18 Applications Information ANALOG INPUT Pseudo-Differential Unipolar Input Range The analog inputs of the LTC2389-18 can be pin configured to accept one of three input voltage ranges: fully differential (±4.096V), pseudo-differential unipolar (0V to 4.096V), and pseudo-differential bipolar (±2.048V).
LTC2389-18 Applications Information Input Filtering The noise and distortion of the buffer amplifier and other supporting circuitry must be considered since they add to the ADC noise and distortion. A buffer amplifier with low noise density must be selected to minimize SNR degradation. A filter network should be placed between the buffer output and ADC input to both minimize the noise contribution of the buffer and reduce disturbances reflected into the buffer from ADC sampling transients.
LTC2389-18 Applications Information 4.096V 0V LOWPASS FILTERS 1/2 LT6201 0V – + 4.096V 10Ω 49.9Ω IN+ 1nF 0V 4.096V LTC2389-18 + – 0V 4.096V 10Ω 1nF 49.9Ω IN– 238918 F05a 1/2 LT6201 0V 2.048V Figure 5a. LT6201 Buffering a Fully-Differential or Single-Ended Signal Source –60 –80 –100 –120 0 SNR = 95.2dB –20 THD = –111dB SINAD = 95.1dB –40 SFDR = 112dB AMPLITUDE (dBFS) 0 SNR = 94.6dB –20 THD = –112dB SINAD = 94.5dB –40 SFDR = 113dB AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 SNR = 99.
LTC2389-18 Applications Information In applications where slightly degraded SNR and THD performance is acceptable, it is possible to drive the LTC2389-18 using the lower power LT6231 ADC driver configured as two unity-gain buffers, as shown in Figure 6a. The RC time constant of the output lowpass filter is larger in this topology to limit the high frequency noise contribution of the LT6231. As shown in the FFT plots in Figures 6b-6d, this circuit achieves 99.
LTC2389-18 Applications Information Single-Ended to Differential Conversion In some applications it may be desirable to convert a single-ended unipolar or bipolar signal to a fully-differential signal prior to driving the LTC2389-18 to take advantage of the higher SNR of the LTC2389-18 in fully differential input mode. The LT6201 ADC driver configured in the topology shown in Figure 7a can be used to convert a 0V to 4.096V single-ended input signal to a fully-differential ±4.096V output signal.
LTC2389-18 Applications Information An alternate single-ended to differential topology employing the LT6231 followed by the LT6201 is shown in Figure 8a. This topology enables additional band-limiting of the wideband noise of the single-ended to differential 4.096V 4.096V 0V + – 1/2 LT6231 LOWPASS FILTERS A 0V 1k 50Ω VCM = 2.048V LOWPASS FILTERS B 49.
LTC2389-18 Applications Information Single-Ended Unipolar and Bipolar Inputs LT6200 combines fast settling and good DC linearity with a 0.95nV/√Hz input-referred noise density, enabling it to achieve the full ADC data sheet SNR and THD specifications in both pseudo-differential input modes, as shown in the FFT plots in Figures 9b and 9c. The LTC2389-18 accepts both single-ended unipolar and single-ended bipolar input signals directly.
LTC2389-18 Applications Information In applications where slightly degraded SNR and THD performance is acceptable, it is possible to drive the LTC2389-18 using the lower power LT6230 ADC driver configured as a unity-gain buffer, as shown in Figure 10a. The RC time constant of the output lowpass filter is larger in this topology to limit the high frequency noise contribution of the LT6230.
LTC2389-18 Applications Information ADC REFERENCE DYNAMIC PERFORMANCE A low noise, low temperature drift reference is critical to achieving the full data sheet performance of the ADC. The LTC2389-18 provides an excellent internal reference with a ±20ppm/°C (maximum) temperature coefficient. If even better accuracy is required, an external reference can be used. In both cases, the high speed, low noise internal reference buffer is employed and cannot be bypassed.
LTC2389-18 Applications Information Total Harmonic Distortion (THD) Power Supply Sequencing Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL /2). THD is expressed as: The LTC2389-18 does not have any specific power supply sequencing requirements.
LTC2389-18 Applications Information Power Shutdown Mode When PD is tied high, the LTC2389-18 enters power shutdown. In this state, all internal functions, including the reference, are turned off and subsequent conversion requests are ignored. Before entering power shutdown, the digital output data should be read.
LTC2389-18 Applications Information DIGITAL INTERFACE To accommodate a variety of application-specific processor and FPGA data bus widths, the LTC2389-18 output bus may be configured to operate in either 18-bit parallel, 16-bit parallel, 8-bit parallel or serial modes, as described in Table 1. The flexible OVDD supply allows the LTC2389-18 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems.
LTC2389-18 Applications Information MODE[1:0] = 00 tCNVSTL CS = 0, MODE[1:0] = 00 CNVST, CS tCNVSTL CNVST BUSY BUSY tCONV tDDBUSYL tBUSYLH DATA BUS D[17:0] CURRENT CONVERSION PREVIOUS CONVERSION DATA BUS D[17:0] Hi-Z Hi-Z PREVIOUS CONVERSION 238918 F14 238918 F16 tDIS tEN Figure 14. Read the Parallel Data Continuously. The Data Bus Is Always Driven and Cannot Be Shared Figure 16.
LTC2389-18 Applications Information MODE[1:0] = 11 SCK STARTS LOW tDSCK CS BUSY tSCK tSCKL tSCKH SCK 1 2 4 3 17 18 19 20 tDSDO, tHSDO SDO (ADC 2) Hi-Z tEN D15 D1 D0 X17 X16 tHSDI tSSDI SDI (ADC 2) D16 D17 Hi-Z X17 X16 X15 MODE[1:0] = 11 X1 X0 SCK STARTS HIGH tDSCK CS BUSY tSCK tSCKL tSCKH SCK 1 2 3 4 17 18 19 20 tDSDO, tHSDO SDO (ADC 2) Hi-Z D17 tEN tSSDI SDI (ADC 2) Hi-Z D16 D15 D1 D0 X17 X16 tHSDI X17 X16 X15 X1 X0 CNVST IN CS IN SCK IN LTC238
LTC2389-18 Applications Information Serial Bus Configuration In applications where a serial bus is required to minimize the data bus width, the LTC2389-18 is capable of providing each conversion result R[17:0] serially on pin D12/SDO. To select this bus configuration, pins MODE = MODE[1:0] should be driven to MODE = 11, as described in Table 1. As shown in Figure 19, the serial output data is presented on the SDO pin in response to an external shift clock input applied to the SCK pin.
LTC2389-18 Applications Information BOARD LAYOUT To obtain the best performance from the LTC2389-18, a printed circuit board (PCB) is recommended. Layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC.
LTC2389-18 Applications Information 238918 F22 Partial Layer 1 Component Side 238918 F23 Partial Layer 2 Ground Plane 238918f 35
LTC2389-18 Applications Information 238918 F24 Partial Layer 3 Power Plane 238918 F25 Partial Layer 4 Bottom Layer 238918 F26 Bottom Silk Partial 238918f 36
AIN0V - 4.096V AIN+ 0V - 4.096V CLK 100MHz MAX 3.3VPP J3 J2 0 Ohm R41 -IN JP2 0 Ohm R14 +IN JP1 0.1uF R6 49.9 1% 1206 C5 AC AC DC R4 1K R2 1K C12 DC 10uF C16 (OPT) 10uF C32 (OPT) C31 2 3 5 (OPT) C17 R42 (OPT) R40 (OPT) INT CM JP3 EXT C33 (OPT) C30 10uF 330pF 402 1% C25 R29 VCMX2 R19 (OPT) R11 (OPT) C10 10uF U3 NC7SZ04P5X 4 C2 0.1uF C40 0.1uF 0402 3 2 1 C3 0.1uF C43 0.
LTC2389-18 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. LX Package 48-Lead Plastic LQFP (7mm × 7mm) (Reference LTC DWG # 05-08-1760 Rev Ø) 7.15 – 7.25 9.00 BSC 5.50 REF 7.00 BSC 48 0.50 BSC 1 2 48 SEE NOTE: 4 1 2 9.00 BSC 5.50 REF 7.00 BSC 7.15 – 7.25 0.20 – 0.30 A A PACKAGE OUTLINE C0.30 – 0.50 1.30 MIN RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 1.60 1.35 – 1.45 MAX 11° – 13° R0.
LTC2389-18 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UK Package 48-Lead Plastic QFN (7mm × 7mm) (Reference LTC DWG # 05-08-1704) 0.70 ±0.05 5.15 ± 0.05 5.50 REF 6.10 ±0.05 7.50 ±0.05 (4 SIDES) 5.15 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.115 TYP 47 48 0.40 ± 0.
LTC2389-18 Typical Application ADC Driver: Single-Ended Input to Differential Output 4.096V 4.096V 0V + – 1/2 LT6201 0V 330pF 49.9Ω 10Ω 330pF 402Ω 1nF IN+ 1nF IN– LTC2389-18 402Ω 1/2 LT6201 + – LOWPASS FILTERS – + 10Ω 49.9Ω 238918 TA02 4.096V VCM = 2.048V 0V Related Parts PART NUMBER DESCRIPTION COMMENTS ADCs LTC2379-18/LTC2378-18/ 18-Bit,1.6Msps/1Msps/500ksps/250ksps Serial, LTC2377-18/LTC2376-18 Low Power ADC 2.5V Supply, Differential Input, 101.