Datasheet
LTC2389-16
6
238916f
Figure 1. Voltage Levels for Timing Specifications
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above
V
DD
or OV
DD
, they will be clamped by internal diodes. This product can
handle input currents up to 100mA below ground, or above V
DD
or OV
DD
,
without latchup.
Note 4: V
DD
= 5V, OV
DD
= 5V, V
REF
= 4.096V external reference,
f
SMPL
= 2.5MHz, unless otherwise noted.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Fully differential zero-scale error is the offset voltage measured
from –0.5LSB when the output code flickers between 0000 0000 0000
0000 and 1111 1111 1111 1111 in two’s complement format. Unipolar
zero-scale error is the offset voltage measured from 0.5LSB when the
output code flickers between 0000 0000 0000 0000 and 0000 0000
0000 0001. Bipolar zero-scale error is the offset voltage measured
from
–0.5LSB when the output code flickers between 0000 0000 0000 0000 and
1111 1111 1111 1111. Fully differential full-scale error is the worst-case
deviation of the first and last code transitions from ideal and includes the
effect of offset error. Unipolar full-scale error is the deviation of the last
code transition from ideal and includes the effect of offset error. Bipolar
full-scale error is the worst-case deviation of the first and last code
transitions from ideal and includes the effect of offset error.
Note 8:
All specifications in dB are referred to a full-scale ±4.096V (fully
differential), 0V to 4.096V (pseudo-differential unipolar), or ±2.048V
(pseudo-differential bipolar) input with a 4.096V reference voltage.
Note 9: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 10: Guaranteed by design, not subject to test.
Note 11: A t
SCK
period of 10ns minimum allows a shift clock frequency of
up to 100MHz for rising capture.
0.8 • OV
DD
0.2 • OV
DD
50% 50%
238916 F01
0.2 • OV
DD
0.8 • OV
DD
0.2 • OV
DD
0.8 • OV
DD
t
DELAY
t
WIDTH
t
DELAY
t
HSDI
SDI Hold Time From SCK↓
l
1 ns
t
DSDO
SDO Data Valid Delay From SCK↑
C
L
= 15pF
l
9 ns
t
HSDO
SDO Data Remains Valid Delay From SCK↑
C
L
= 15pF
l
1 ns
t
DDBUSYL
Data Valid to BUSY↓
C
L
= 15pF
l
1 ns
t
EN
Bus Enable Time After CS↓
l
11 ns
t
DDA1
Data Valid Delay From A1 Transition C
L
= 15pF
l
8 ns
t
DIS
Bus Relinquish Time After CS↑
l
11 ns
timing characteristics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 4)