Datasheet

LTC2389-16
34
238916f
applications inFormation
Partial Top Silkscreen
238916 F20
BOARD LAYOUT
To obtain the best performance from the LTC2389-16, a
printed circuit board (PCB) is recommended. Layout for
the printed circuit board should ensure the digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital clocks
or signals alongside analog signals or underneath the ADC.
Pin Compatibility with LTC2389-18
To ensure a board layout intended for use with the
LTC2389-16 is also compatible with 18-bit versions of
the LTC2389 family, the design should maintain the ability
to drive Pins 4 (MODE0) and 5 (MODE1) to both logic high
and logic low levels, to dynamically drive Pins 7 (A0) and 8
(A1) to both logic high and logic low levels, and to read
dynamic data driven by the LTC2389-18 on Pins 7 (A0)
and 8 (A1). Additionally, if the 8-bit parallel bus configur-
ation is used, the upper byte Pins 28 through 21 (D[15:8])
of the output data bus should be used to read the conver-
sion results. Simplifications to these constraints are
possible based on the specific application. For further
details on the operation of the LTC2389-18, please refer
to the associated data sheet.
Recommended Layout
The following is
an example
of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are shielded by ground. For
more details and information refer to DC1826A-E, the
evaluation kit for the LTC2389-16.