Datasheet

LTC2389-16
29
238916f
Figure 13. Supply Current vs Sampling Frequency. Power Dissipation
of the LTC2389-16 Decreases with Decreasing Sampling Frequency
1 100 100010 10000
SAMPLING FREQUENCY (kHz)
15
SUPPLY CURRENT (mA)
25
0
5
35
20
30
10
I
OVDD
I
VDD
238916 F13
Power Shutdown Mode
When PD is tied high, the LTC2389-16 enters power
shutdown. In this state, all internal functions, including
the reference, are turned off and subsequent conversion
requests are ignored. Before entering power shutdown, the
digital output data should be read. If a request for power
shutdown occurs during a conversion, the conversion will
finish and then the device will power down, but the data from
that conversion should be read only after power shutdown
mode has ended. In this mode, power consumption drops
to a typical value of 75μW from 162.5mW. This mode can
be used if the LTC2389-16 is inactive for a long period of
time and the user wants to minimize power dissipation.
Recovery From Power Shutdown Mode
To end the power shutdown and begin powering up the
internal circuitry, return the PD pin to a low level. If the
internal reference is used, the 2.3kΩ output impedance
with the 1μF bypass capacitor on the REFIN/REFOUT pins
will be the main time constant for the power-on recovery
time. If an external reference is used, typically allow 5ms
for recovery before initiating a new conversion.
Power Dissipation vs Sampling Frequency
When nap mode is employed, the
power dissipation of
the
LTC2389-16 will decrease as the sampling frequency
is reduced, as shown in Figure 13. This decrease in
average power dissipation occurs because a portion of
the circuitry on the LTC2389-16 is turned off during nap
mode and the fraction of the conversion cycle (t
CYC
) spent
napping increases as the sampling frequency (f
SMPL
) is
decreased.
TIMING AND CONTROL
CNVST Timing
The LTC2389-16 conversion is controlled by CNVST. A
falling edge on CNVST initiates the conversion process,
which once begun, cannot be restarted until the con-
version is complete. For optimum performance, CNVST
should be driven by a clean, low jitter signal and transi-
tions on data I/O lines should be avoided leading up to the
falling edge of CNVST. Converter status is indicated by the
BUSY output, which remains high while the conversion
is in progress. Once CNVST is brought low to begin a
conversion, it should be returned high either within 40ns
from the start of the conversion or after the conversion
is complete to ensure no errors occur in the digitized
results. The CNVST timing required to take advantage of
the reduced power nap mode of operation is described in
the Nap
Mode section.
Internal Conversion Clock
The
LTC2389-16 has an internal clock that is trimmed to
achieve a maximum conversion time of 310ns. No external
adjustments are required and with a minimum acquisition
time of 77ns, a throughput performance of 2.5Msps is
guaranteed in the parallel output modes.
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