Datasheet

LTC2389-16
14
238916f
is the serial data input, which can be used to daisy chain
two or more converters on a single SDO line. The digital
data level on SDI is output on SDO with a delay of 16 SCK
periods after the start of the read sequence. Logic levels
are determined by OV
DD
.
D10/SDO (Pin 23): Data Bit 10/Serial Data Output. When
MODE0 = 0, this pin is bit 10 of the parallel data output
bus, as described in Table 1. When MODE0 = 1, this pin
is the serial data output line, which serially outputs the
result of the most recent conversion clocked by SCK. The
data is output MSB first on the rising edge of SCK. The
data format is determined by the logic levels of pins PD/FD
and OB/2C, as described in Table 2. Logic levels are
determined by OV
DD
.
D11/SCK (Pin 24): Data Bit 11/Serial Clock Input. When
MODE0 = 0, this pin is bit 11 of the parallel data output
bus, as described in Table 1. When MODE0 = 1, this pin
this is the serial clock input. Logic levels are determined
by OV
DD
.
D12 (Pin 25): Data Bit 12. When MODE0 = 0, this pin
is bit 12 of the parallel data output bus, as described in
Table 1. Logic
levels are determined by OV
DD
.
D13 (Pin 26): Data Bit 13. When MODE0 = 0, this pin
is bit 13 of the parallel data output bus, as described in
Table 1. Logic levels are determined by OV
DD
.
D14 (Pin 27): Data Bit 14. When MODE0 = 0, this pin
is bit 14 of the parallel data output bus, as described in
Table 1. Logic levels are determined by OV
DD
.
D15 (Pin 28): Data Bit 15. When MODE0 = 0, this pin
is bit 15 of the parallel data output bus, as described in
Table 1. Logic levels are determined by OV
DD
.
BUSY (Pin 29): Busy Output. This pin transitions low to
high at the start of each conversion and stays high until
the conversion is complete. The falling edge of BUSY can
be used as the data-ready clock signal. Logic levels are
determined by OV
DD
.
pin Functions
Table 1. Data Bus Configuration Table. Use Input MODE0 to Select Bus Configuration Based on Application Bus Width.
In the 16-Bit/8-Bit Parallel Configuration, Input A1 Controls Mapping of Upper and Lower Bytes of Conversion Result R[15:0] Onto
Data Bus Pins D[15:0]. Shaded Cells Denote Bidirectional Pins Configured as Inputs.
BUS CONFIGURATION MODE0 A1 D[15:12] D11 D10 D9 D8 D[7:0]
16-Bit/8-Bit Parallel
0 0 R[15:8] R[7:0]
0 1 R[7:0] R[15:8]
Serial 1 X All Hi-Z SCK SDO SDI All Hi-Z