Datasheet

LTC2389-16
13
238916f
pin Functions
GND (Pins 1, 17, 20, 35, 41, 44, 48, Exposed Pad
Pin 49 (QFN Only)): Ground. Solder all GND pins and
exposed pad to the ground plane.
V
DD
(Pins 2, 3, 19, 40, 45, 46, 47): 5V Power Supply.
The range of V
DD
is 4.75V to 5.25V. Bypass V
DD
network
to GND with a 0.1μF ceramic capacitor close to each pin
and a 10μF ceramic capacitor in parallel.
MODE0 (Pin 4): Data Bus Configuration Input. This pin,
in conjunction with Pin 8 (A1), controls the parsing and
presentation of conversion results on the output data bus.
Based on the state of MODE0, the bus is configured to
provide either 16-bit/8-bit parallel (MODE0 = 0), or serial
(MODE0 = 1) data, as described in Table 1. Digital outputs
that are not active in a particular mode become Hi-Z. Logic
levels are determined by OV
DD
. For information regarding
pin compatibility with 18-bit versions of the LTC2389 family,
refer to the Pin Compatibility with LTC2389-18 section.
MODE1 (Pin 5): Data Bus Configuration Input. This pin is
reserved for use in 18-bit versions of the LTC2389 family,
and for 16-bit versions of the family it should be driven to
a logic low level. Logic levels are determined by OV
DD
. For
information regarding pin compatibility with 18-bit versions
of
the LTC2389 family, refer to the Pin Compatibility with
LTC2389-18 section.
OB/2C (Pin 6): Offset Binary/ Two’s Complement Input.
This pin, in conjunction with Pin 30 (PD/FD), controls the
analog input range of the converter and the binary format
of the conversion result, as described in Table 2. Logic
levels are determined by OV
DD
.
A0 (Pin 7): Address Bit 0 Input. This pin is reserved
for use in 18-bit versions of the LTC2389 family, and
for 16-bit versions of the family it should be driven to a
logic low level. Logic levels are determined by OV
DD
. For
information regarding pin compatibility with 18-bit versions
of the LTC2389 family, refer to the Pin Compatibility with
LTC2389-18 section.
A1 (Pin 8): Address Bit 1 Input. This pin, in conjunction
with Pin 4 (MODE0), controls the parsing and presentation
of conversion results on the parallel output data bus. When
MODE0 = 0, the bus is configured to provide 16-bit/8-bit
parallel data, and the logic input A1 determines which
segment of the conversion result is driven on the upper
and lower bytes of the bus, as described in Table 1. When
MODE0 = 1, the output data bus is configured to provide
serial data, and the logic input A1 has no effect on the
parsing
or presentation of the serial data. Logic levels
are determined by OV
DD
. For information regarding pin
compatibility with 18-bit versions of the LTC2389 family,
refer to the Pin Compatibility with LTC2389-18 section.
D0 (Pin 9): Data Bit 0. When MODE0 = 0, this pin is bit 0
of the parallel data output bus, as described in Table 1.
Logic levels are determined by OV
DD
.
D1 (Pin 10): Data Bit 1. When MODE0 = 0, this pin is bit 1
of the parallel data output bus, as described in Table 1.
Logic levels are determined by OV
DD
.
D2 (Pin 11): Data Bit 2. When MODE0 = 0, this pin is bit 2
of the parallel data output bus, as described in Table 1.
Logic levels are determined by OV
DD
.
D3 (Pin 12): Data Bit 3. When MODE0 = 0, this pin is bit 3
of the parallel data output bus, as described in Table 1.
Logic levels are determined by OV
DD
.
D4 (Pin 13): Data Bit 4. When MODE0 = 0, this pin is bit 4
of the parallel data output bus, as described in Table 1.
Logic levels are determined by OV
DD
.
D5 (Pin 14): Data Bit 5. When MODE0 = 0, this pin is bit 5
of the parallel data output bus, as described in Table
1.
Logic levels are determined by OV
DD
.
D6 (Pin 15): Data Bit 6. When MODE0 = 0, this pin is bit 6
of the parallel data output bus, as described in Table 1.
Logic levels are determined by OV
DD
.
D7 (Pin 16): Data Bit 7. When MODE0 = 0, this pin is bit 7
of the parallel data output bus, as described in Table 1.
Logic levels are determined by OV
DD
.
OV
DD
(Pin 18): I/O Interface Power Supply. The range of
OV
DD
is 1.71V to 5.25V. Bypass OV
DD
to GND close to the
pin with a 0.1μF and a 10μF ceramic capacitor in parallel.
D8 (Pin 21): Data Bit 8. When MODE0 = 0, this pin is bit 8
of the parallel data output bus, as described in Table 1.
Logic levels are determined by OV
DD
.
D9/SDI (Pin 22): Data Bit 9/Serial Data Input. When
MODE0 = 0, this pin is bit 9 of the parallel data output
bus, as described in Table 1. When MODE0 = 1, this pin