Datasheet

LTC2377-20
9
237720f
For more information www.linear.com/LTC2377-20
TiMing DiagraM
applicaTions inForMaTion
POWER-DOWNCONVERT
ACQUIREHOLD
D17D19 D18 D2 D1 D0
SDO
SCK
CNV
CHAIN, RDL/SDI = 0
BUSY
237720 TD01
Conversion Timing Using the Serial Interface
OVERVIEW
The LTC2377-20 is a low noise, low power, high speed
20-bit successive approximation register (SAR) ADC.
Operating from a single 2.5V supply, the LTC2377-20
supports a large and flexible ±V
REF
fully differential input
range with V
REF
ranging from 2.5V to 5.1V, making it ideal
for high performance applications which require a wide
dynamic range. The LTC2377-20 achieves ±2ppm INL
maximum, no missing codes at 20 bits and 104dB SNR.
Fast 500ksps throughput with no cycle latency makes
the LTC2377-20 ideally suited for a wide variety of high
speed applications. An internal oscillator sets the con-
version time, easing external timing considerations. The
LTC2377-20 dissipates only 10.5mW at 500ksps, while
an auto power-down feature is provided to further reduce
power dissipation during inactive periods.
The LTC2377-20 features a unique digital gain compres-
sion (DGC) function, which eliminates the driver amplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
function that maps zero-scale code from 0V to 0.1 • V
REF
and full-scale code from V
REF
to 0.9 • V
REF
. For a typical
reference voltage of 5V, the full-scale input range is now
0.5V
to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
CONVERTER OPERATION
The LTC2377-20 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN
+
and IN
–
pins
to sample the differential analog input voltage. A rising
edge on the CNV pin initiates a conversion. During the
conversion phase, the 20-bit CDAC is sequenced through a
successive approximation algorithm, effectively comparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g. V
REF
/2, V
REF
/4 … V
REF
/1048576)
using the differential comparator. At the end of conversion,
the CDAC output approximates the sampled analog input.
The ADC control logic then prepares the 20-bit digital
output code for serial transfer.
TRANSFER FUNCTION
The LTC2377-20 digitizes the full-scale voltage of 2 × REF
into 2
20
levels, resulting in an LSB size of 9.5µV with
REF = 5V. Note that 1 LSB at 20 bits is approximately
1ppm. The ideal transfer function is shown in Figure 2.
The output data is in 2’s complement format.
ANALOG INPUT
The analog inputs of the LTC2377-20 are fully differential
in order to maximize the signal swing that
can be digitized.
The
analog inputs can be modeled by the equivalent circuit