Datasheet

LTC2376-20
16
237620f
For more information www.linear.com/LTC2376-20
applicaTions inForMaTion
Auto Power-Down
The LTC2376-20 automatically powers down after a
conversion has been completed and powers up once a
new conversion is initiated on the rising edge of CNV.
During power down, data from the last conversion can
be clocked out. To minimize power dissipation during
power down, disable SDO and turn off SCK. The auto
power-down feature will reduce the power dissipation of
the LTC2376-20 as the sampling frequency is reduced.
Since power is consumed only during a conversion, the
LTC2376-20 remains powered-down for a larger fraction of
the conversion cycle (t
CYC
) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 14.
DIGITAL INTERFACE
The LTC2376-20 has a serial digital interface. The flexible
OV
DD
supply allows the LTC2376-20 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
20MHz, a
250ksps throughput
is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D19 remains valid until the first rising edge of SCK.
The serial interface on the LTC2376-20 is simple and
straightforward to use. The following sections describe the
operation of the LTC2376-20. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy chained.
SAMPLING RATE (kHz)
0 250150 20050 100
0
POWER SUPPLY CURRENT (mA)
2.5
2.0
1.5
1.0
0.5
237620 F14
I
VDD
I
REF
I
OVDD
Figure 14. Power Supply Current of the LTC2376-20
Versus Sampling Rate