Datasheet

LTC2313-14
8
231314fa
For more information www.linear.com/LTC2313-14
T
A
= 25°C, V
DD
= 5V, OV
DD
= 2.5V, f
SMPL
= 2.5Msps,
unless otherwise noted.
pin FuncTions
V
DD
(Pin 1): Power Supply. The ranges of V
DD
are 2.7V
to 3.6V and 4.75V to 5.25V. Bypass V
DD
to GND with a
2.2µF ceramic chip capacitor.
REF (Pin 2): Reference Input/Output. The REF pin volt
-
age defines the input span of the ADC, 0V to V
REF
. By
default, REF is an output pin and produces a reference
voltage V
REF
of either 2.048V or 4.096V depending on
V
DD
(see Table 2). Bypass to GND with a 2.2µF, low ESR,
high quality ceramic chip capacitor. The REF pin may be
overdriven with a voltage at least 50mV higher than the
internal reference voltage output.
GND (Pin 3): Ground. The GND pin must be tied directly
to a solid ground plane.
A
IN
(Pin 4): Analog Input. A
IN
is a single-ended input with
respect to GND with a range from 0V to V
REF
.
OV
DD
(Pin 5): I/O Interface Digital Power. The OV
DD
range
is 1.71V to 5.25V. This supply is nominally set to the
same supply as the host interface (1.8V, 2.5V, 3.3V or
5V). Bypass to GND with a 2.2µF ceramic chip capacitor.
SDO (Pin 6): Serial Data Output. The A/D conversion result
is
shifted out on SDO as a serial data stream with the MSB
first
through the LSB last. The data stream consists of 14
bits of conversion data followed by trailing zeros. There
is no cycle latency. Logic levels are determined by OV
DD
.
SCK (Pin 7): Serial Data Clock Input. The SCK serial clock
synchronizes the serial data transfer. SDO data transitions
on the falling edge of SCK. Logic levels are determined
by OV
DD
.
CONV (Pin 8): Convert Input. This active high signal starts
a conversion on the rising edge. The conversion is timed
via an internal oscillator. The device automatically powers
down following the conversion process. The SDO pin is
in high impedance when CONV is a logic high. Bringing
CONV low enables the SDO pin and outputs the MSB.
Subsequent bits of the conversion data are read out seri
-
ally on
the falling edge of SCK. A logic low on CONV also
places
the sample-and-hold into sample mode. Logic levels
are determined by OV
DD
.
Output Supply Current (I
OVDD
)
vs Output Supply Voltage (OV
DD
)
Supply Current (I
VDD
)
vs Supply Voltage (V
DD
)
Typical perForMance characTerisTics
OUTPUT SUPPLY VOLTAGE (V)
1.7
0
OUTPUT SUPPLY CURRENT (mA)
0.5
1.0
2.5
2.0
1.5
2.92.3 4.13.5 4.7 5.3
231314 G19
SUPPLY VOLTAGE (V)
2.6
3.75
SUPPLY CURRENT (mA)
4.50
4.25
4.00
4.75
5.00
5.25
5.75
5.50
2.9 3.83.53.2 4.1 4.74.4 5.35.0
231314 G18
OPERATION
NOT ALLOWED