Datasheet

LTC2313-12
9
231312fa
For more information www.linear.com/LTC2313-12
TiMing DiagraMs
block DiagraM
231312 BD
4
–
+
S/H
2.5V LDO
2×/4×
1.024V
BANDGAP
TIMING
LOGIC
1
6
7
8
THREE-STATE
SERIAL
OUTPUT
PORT
12-BIT SAR ADC
2
3
A
IN
REF
V
DD
OV
DD
2.2µF
GND
ANALOG
INPUT RANGE
0V TO V
REF
ANALOG SUPPLY
3V OR 5V
I/O INTERFACE SUPPLY
RANGE 1.8V TO 5V
5
2.2µF2.2µF
SDO
SCK
CONV
TS8 PACKAGE
ALL CAPACITORS UNLESS
NOTED ARE HIGH QUALITY,
CERAMIC CHIP TYPE
231312 TD04231312 TD03
231312 TD02231312 TD01
Hi-Z
MSB
CONV
OV
DD
/2
SDO
V
OH
t
3
Hi-Z
CONV
OV
DD
/2
SDO
t
8
V
OH
V
OL
SCK
OV
DD
/2
SDO
t
7
V
OH
V
OL
SCK
OV
DD
/2
SDO
t
4
Figure 1. SDO Enabled After CONV↓
Figure 3. SDO Data Valid Hold After SCK↓
Figure 2. SDO Into Hi-Z After CONV↑
Figure 4. SDO Data Valid Access After SCK↓
V
OL