Datasheet

LTC2313-12
16
231312fa
For more information www.linear.com/LTC2313-12
applicaTions inForMaTion
Intermodulation Distortion (IMD)
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies f
a
and f
b
are ap-
plied to the ADC input, nonlinearities in the ADC transfer
function
can create distortion products at the sum and
difference frequencies m • f
a
± n • f
b
, where m and n = 0,
1, 2, 3, etc. For example, the 2nd order IMD terms include
(f
a
± f
b
). If the two input sine waves are equal in magnitude,
the value (in decibels) of the 2nd order IMD products can
be expressed by the following formula:
IMD(f
a
± f
b
) = 20 • log[V
A
(f
a
± f
b
)/V
A
(f
a
)]
The LTC2313-12 has excellent IMD, as shown in Figure 15.
Figure 15. LTC2313-12 IMD Plot
231312 F15
INPUT FREQUENCY (kHz)
MAGNITUDE (dB)
0 1250
500250
750 1000
0
–20
f
a
f
b
2f
a
– f
b
2f
b
– f
a
f
b
– f
a
–40
–60
–80
–100
–120
–140
–160
V
DD
= 5V
f
s
= 2.5Msps
f
a
= 255.421kHz
f
b
= 285.421kHz
IMD
2
(f
b
– f
a
) = –80.4dBc
IMD
3
(2f
b
– f
a
) = –91.8dBc
f
a
+ f
b
Full-Power and –3dB Input Linear Bandwidth
The full-power bandwidth is the input frequency at which
the amplitude of the reconstructed fundamental is reduced
by 3dB for a full-scale input signal.
The –3dB linear bandwidth is the input frequency at which
the SINAD has dropped to 68dB (11 effective bits). The
LTC2313-12 has
been designed to optimize the input
bandwidth, allowing the ADC to under-sample input signals
with frequencies above the converter’s Nyquist frequency.
The noise floor stays very low at high frequencies and
SINAD becomes dominated by distortion at frequencies
beyond Nyquist.
Recommended Layout
To obtain the best performance from the LTC2313-12 a
printed circuit board is required. Layout for the printed
circuit board (PCB) should ensure the digital and analog
signal lines are separated as much as possible. In par
-
ticular, care
should be taken not to run any digital clocks
or
signals alongside analog signals or underneath the
ADC. Figures 16 through 20 are an example of a recom
-
mended PCB layout. A single solid ground plane is used.
Bypass capacitors to the supplies are placed as close as
possible to the supply pins. Low impedance common
returns for these bypass capacitors are essential to the
low noise operation of the ADC. The analog input traces
are screened by ground. For more details and information
refer to DC1563, the evaluation kit for the LTC2313-12.
Bypassing Considerations
High quality ceramic bypass capacitors should be used at
the V
DD
, OV
DD
and REF pins. For optimum performance, a
2.2µF ceramic chip capacitor should be used for the V
DD
and OV
DD
pins. The recommended bypassing for the REF
pin is also a low ESR, 2.2µF ceramic chip capacitor. The
traces connecting the pins and the bypass capacitors must
be kept as short as possible and should be made as wide
as possible avoiding the use of vias.
All analog circuitry grounds should be terminated at the
LTC2313-12. The ground return from the LTC2313-12 to
the power supply should be low impedance for noise free
operation. Digital circuitry grounds must be connected to
the digital supply common.
Spurious Free Dynamic Range (SFDR)
The spurious free dynamic range is the largest spectral
component excluding DC and the input signal. This value
is expressed in decibels relative to the RMS value of a
full-scale input signal.