Datasheet

LTC2313-12
10
231312fa
For more information www.linear.com/LTC2313-12
applicaTions inForMaTion
Overview
The LTC2313-12 is a low noise, high speed, 12-bit succes-
sive approximation
register (SAR) ADC. The LTC2313-12
operates from a single 3V or 5V supply and provides a
low drift (20ppm/°C maximum), internal reference and
reference buffer. The internal reference buffer is automati
-
cally configured
with a 2.048V span in low supply range
(2.7V to 3.6V) and with a 4.096V span in the high supply
range (4.75V to 5.25V). The LTC2313-12 samples up to
a 2.5Msps rate and supports a 90MHz serial data read
clock. The LTC2313-12 achieves excellent dynamic per
-
formance (72.6dB SINAD
, –84
dB THD) while dissipating
only 25mW from a 5V supply at the 2.5Msps conversion
rate. The LTC2313-12 outputs the conversion data with
no cycle latency onto the SDO pin. The SDO pin output
logic levels are supplied by the dedicated OV
DD
supply pin
which has a wide supply range (1.71V to 5.25V) allowing
the LTC2313-12 to communicate with 1.8V, 2.5V, 3V or 5V
systems. The LTC2313-12 automatically switches to nap
mode following the conversion process to save power. The
device also provides a sleep power-down mode through
serial interface control to reduce power dissipation during
long inactive
periods.
Serial Interface
The
LTC2313-12 communicates with microcontrollers,
DSPs and other external circuitry via a 3-wire interface. A
rising CONV edge starts the conversion process which is
timed via an internal oscillator. Following the conversion
process the device automatically switches to nap mode
to save power as shown in Figure 7. This feature saves
considerable power for the LTC2313-12 operating at
lower sampling rates. As shown in Figures 5 and 6, it is
recommended to hold SCK static low or high during t
CONV
.
A falling CONV edge enables SDO and outputs the MSB.
Subsequent SCK falling edges clock out the remaining data
as shown in Figures 5 and 6. CONV must be held high for
the minimum conversion time, t
CONV(MIN)
.Data is serially
output MSB first through LSB last, followed by trailing
zeros if further SCK falling edges are applied.
Serial Data Output (SDO)
The SDO output is always forced into the high imped
-
ance state
while CONV is high. The falling edge of CONV
enables
SDO and also places the sample and hold into
sample mode. The A/D conversion result is shifted out
on the SDO pin as a serial data stream with the MSB first.
The MSB is output
on SDO on the falling edge of CONV.
Delay
t
3
is the data valid access time for the MSB. The
following 11 bits of conversion data are shifted out on
SDO on the falling edge of SCK. Delay t
4
is the data valid
access time for output data shifted out on the falling edge
of SCK. There is no data latency. Subsequent falling SCK
edges applied after the LSB is output will output zeros
indefinitely on the SDO pin.
The output swing on the SDO pin is controlled by the
OV
DD
pin voltage and supports a wide operating range
from 1.71V to 5.25V independent of the V
DD
pin voltage.
Power Considerations
The LTC2313-12 provides two sets of power supply pins:
the analog power supply (V
DD
) and the digital input/output
interface power supply (OV
DD
). The flexible OV
DD
supply
allows the LTC2313-12 to communicate with any digital
logic operating between 1.8V and 5V, including 2.5V and
3.3V systems.
Entering Nap/Sleep Mode
Pulsing CONV two times and holding SCK static places the
LTC2313-12 into nap mode. Pulsing CONV four times and
holding SCK static places the LTC2313-12 into sleep mode.
In sleep mode, all bias circuitry is
shut down,
including the
internal bandgap and reference buffer, and only leakage
currents remain (0.2µA typical). Because the reference
buffer is externally bypassed with a large capacitor (2.2µF),
the LTC2313-12 requires a significant wait time (1.1ms) to
recharge this capacitance before an accurate conversion
can be made. In contrast, nap mode does not power down
the internal bandgap or reference buffer allowing for a fast
wake-up and accurate conversion within one conversion clock
cycle. Supply current during nap mode is nominally 2mA.