Datasheet

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LTC2313-12

231312fa

For more information www.linear.com/LTC2313-12

Typical applicaTion

FeaTures DescripTion

12-Bit, 2.5Msps Serial

Sampling ADC in TSOT

The LTC

2313-12 is a 12-bit, 2.5Msps, serial sampling

A/D converter that draws only 5mA from a single 3V or

5V supply. The LTC2313-12 contains an integrated low

drift reference and reference buffer providing a low cost,

high performance (20ppm/°C maximum) and space sav

ing solution

. The LTC2313-12 achieves outstanding AC

per

formance of 72.6dB SINAD and –84dB THD while

sampling at 2.5Msps. The extremely high sample rate-to-

power ratio makes the LTC2313-12 ideal for compact, low

power, high speed systems. The supply current decreases

at lower sampling rates as the device automatically enters

nap mode after conversions.

The LTC2313-12 has a high speed SPI-compatible serial

interface that supports 1.8V, 2.5V, 3V and 5V logic. The

fast 2.5Msps throughput with no cycle latency makes

the LTC2313-12 ideally suited for a wide variety of high

speed applications.

Complete 14-/12-Bit Pin-Compatible SAR ADC Family

500ksps 2.5Msps 4.5Msps 5Msps

14-Bit LTC2312-14 LTC2313-14 LTC2314-14

12-Bit LTC2312-12 LTC2313-12 LTC2315-12

Power 3V/5V 9mW/15mW 14mW/25mW 18mW/31mW 19mW/32mW

applicaTions

2.5Msps Throughput Rate

No Cycle Latency

Guaranteed 12-Bit No Missing Codes

Single 3V or 5V Supply

Low Noise: 73dB SNR

Low Power: 14mW at 2.5Msps and 3V Supply

Low Drift (20ppm/°C Maximum) 2.048V or 4.096V

Internal Reference

Sleep Mode with < 1µA Typical Supply Current

Nap Mode with Quick Wake-Up < 1 Conversion

Separate 1.8V to 5V Digital I/O Supply

High Speed SPI-Compatible Serial I/O

Guaranteed Operation from –40°C to 125°C

8-Lead TSOT-23 Package

Communication Systems

High Speed Data Acquisition

Handheld Terminal Interface

Medical Imaging

Uninterrupted Power Supplies

Battery Operated Systems

Automotive

L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

5V Supply, Internal Reference, 2.5Msps, 12-Bit Sampling ADC 16k Point FFT, f

= 2.5Msps, f

= 497kHz

231312 TA01b

INPUT FREQUENCY (kHz)

AMPLITUDE (dBFS)

0 1000

500250

750

–20

–40

–60

–80

–100

–120

–140

–160

= 5V

SNR = 73dBFS

SINAD = 72.6dBFS

THD = –84dB

SFDR = 87dB

SERIAL DATA LINK TO

ASIC, PLD, MPU, DSP

OR SHIFT REGISTERS

ANALOG INPUT

0V TO 4.096V

2.2µF

231312 TA01a

GND

REF

SCK

CONV

SDO

LTC2313-12

DIGITAL OUTPUT SUPPLY

1.8V TO 5V

Summary of content (22 pages)

PAGE 1
LTC2313-12 12-Bit, 2.5Msps Serial Sampling ADC in TSOT Description Features n n n n n n n n n n n n n 2.5Msps Throughput Rate No Cycle Latency Guaranteed 12-Bit No Missing Codes Single 3V or 5V Supply Low Noise: 73dB SNR Low Power: 14mW at 2.5Msps and 3V Supply Low Drift (20ppm/°C Maximum) 2.048V or 4.096V Internal Reference Sleep Mode with < 1µA Typical Supply Current Nap Mode with Quick Wake-Up < 1 Conversion Separate 1.
PAGE 2
LTC2313-12 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) Supply Voltage (VDD, OVDD)........................................6V Reference (REF) and Analog Input (AIN) Voltage (Note 3).......................................(–0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 3).... (–0.3V) to (OVDD + 0.3V) Digital Output Voltage.............. (–0.3V) to (OVDD + 0.3V) Power Dissipation................................................100mW Operating Temperature Range LTC2313C..........................
PAGE 3
LTC2313-12 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VAIN Absolute Input Range VIN Input Voltage Range IIN Analog Input DC Leakage Current CIN Analog Input Capacitance CONDITIONS (Note 11) MIN TYP MAX UNITS l –0.05 VDD + 0.
PAGE 4
LTC2313-12 Reference Input/Output The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VREF CONDITIONS VREF Output Voltage 2.7V ≤ VDD ≤ 3.6V 4.75 ≤ VDD ≤ 5.25V VREF Temperature Coefficient l l MIN TYP MAX UNITS 2.040 4.080 2.048 4.096 2.056 4.
PAGE 5
LTC2313-12 ADC Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS fSAMPLE(MAX) Maximum Sampling Frequency fSCK Shift Clock Frequency tSCK Shift Clock Period MIN TYP MAX UNITS (Notes 7, 8) l 2.5 MHz (Notes 7, 8) l 90 MHz l tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV 11.
PAGE 6
LTC2313-12 Typical Performance Characteristics unless otherwise noted. 0.75 0.75 0.50 0.50 0.25 0.25 0.0 –0.25 –0.75 –0.75 16k Point FFT, fS = 2.5Msps fIN = 497kHz –60 –80 –100 –120 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 231312 G02 500 750 INPUT FREQUENCY (kHz) VDD = 5V 71 VDD = 3V 70 231312 G04 –85 74 THD 73 SNR, SINAD (dBFS) RIN/CIN = 50Ω/47pF fS = 2.
PAGE 7
LTC2313-12 Typical Performance Characteristics unless otherwise noted. THD, Harmonics vs Temperature, fIN = 497kHz SNR, SINAD vs Reference Voltage fIN = 497kHz 400 SNR THD 2ND –90 –95 –100 3RD 72 SINAD VDD = 3.6V 71 –105 –110 –55 –35 –15 70 5 25 45 65 85 105 125 TEMPERATURE (°C) 231312 G10 SINAD VDD = 5V SNR Full-Scale Error vs Temperature 2 OPERATION NOT ALLOWED 2.5 3 3.5 4 REFERENCE VOLTAGE (V) VDD = 3.6V OPERATION NOT ALLOWED 250 200 100 4.
PAGE 8
LTC2313-12 Typical Performance Characteristics unless otherwise noted. 5.75 Supply Current (IVDD) vs Supply Voltage (VDD) 2.5 OUTPUT SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 5.50 5.25 5.00 4.75 OPERATION NOT ALLOWED 4.50 4.25 4.00 3.75 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 SUPPLY VOLTAGE (V) 231312 G18 TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 2.5Msps, Output Supply Current (IOVDD) vs Output Supply Voltage (OVDD) 2.0 1.5 1.0 0.5 0 1.7 2.3 2.9 3.5 4.1 4.7 OUTPUT SUPPLY VOLTAGE (V) 5.
PAGE 9
LTC2313-12 Block Diagram 2.2µF 2.2µF ANALOG SUPPLY 3V OR 5V I/O INTERFACE SUPPLY RANGE 1.8V TO 5V 1 5 VDD OVDD 2.5V LDO ANALOG INPUT RANGE 0V TO VREF AIN + 4 12-BIT SAR ADC S/H – THREE-STATE SERIAL OUTPUT PORT SDO 6 REF SCK 2 2.2µF GND 3 2×/4× 7 TIMING LOGIC 1.024V BANDGAP CONV 8 TS8 PACKAGE 231312 BD ALL CAPACITORS UNLESS NOTED ARE HIGH QUALITY, CERAMIC CHIP TYPE Timing Diagrams t3 CONV SDO CONV OVDD/2 Hi-Z MSB VOH VOL Figure 1.
PAGE 10
LTC2313-12 Applications Information Overview Serial Data Output (SDO) The LTC2313-12 is a low noise, high speed, 12-bit successive approximation register (SAR) ADC. The LTC2313-12 operates from a single 3V or 5V supply and provides a low drift (20ppm/°C maximum), internal reference and reference buffer. The internal reference buffer is automatically configured with a 2.048V span in low supply range (2.7V to 3.6V) and with a 4.096V span in the high supply range (4.75V to 5.25V).
PAGE 11
LTC2313-12 Applications Information t9 tACQ-MIN = 11.5 • tSCK + t2 + t9 CONV tCONV-MIN t2 tACQ t6 SCK 1 t8 t3 HI-Z STATE SDO 2 3 t5 B11 4 t4 B10 B9 10 11 12 t7 B8 B1 B0 0 (MSB) tTHROUGHPUT 231312 F05 Figure 5. LTC2313-12 Serial Interface Timing Diagram (SCK Low During tCONV) t9 tACQ-MIN = 11.5 • tSCK + t2 + t9 CONV tCONV-MIN t2 SCK 1 HI-Z STATE SDO 2 3 t5 t3 t8 tACQ t6 B11 4 t4 B10 B9 10 11 12 t7 B8 B1 B0 0 (MSB) tTHROUGHPUT 231312 F06 Figure 6.
PAGE 12
LTC2313-12 Applications Information Exiting Nap/Sleep Mode with high source impedance, a buffer amplifier should be used. The main requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. Settling time must be less than tACQ-MIN (153ns) for full performance at the maximum throughput rate. While choosing an input amplifier, also keep in mind the amount of noise and harmonic distortion the amplifier contributes.
PAGE 13
LTC2313-12 Applications Information critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC2313-12. (More detailed information is available on the Linear Technology website at www.linear.com.) LT6230: 215MHz GBWP, –80dBc Distortion at 1MHz, Unity-Gain Stable, Rail-to-Rail Input and Output, 3.5mA/ Amplifier, 1.1nV/√Hz.
PAGE 14
LTC2313-12 Applications Information buffer must be overdriven in the external reference configuration with a voltage 50mV higher than the nominal reference output voltage in the internal configuration. Using the Internal Reference The internal bandgap and reference buffer are active by default when the LTC2313-12 is not in sleep mode. The reference voltage at the REF pin scales automatically with the supply voltage at the VDD pin. The scaling of the reference voltage with supply is shown in Table 2.
PAGE 15
LTC2313-12 Applications Information 16,384 times. The distribution is Gaussian and the RMS code transition noise is 0.33LSB. This corresponds to a noise level of 73dB relative to a full scale voltage of 4.096V. At the maximum sampling rate of 2.5MHz, the LTC231312 maintains an ENOB above 11.7 bits up to an input frequency of 1MHz. (Figure 14) Dynamic Performance Signal-to-Noise Ratio (SNR) The LTC2313-12 has excellent high speed sampling capability.
PAGE 16
LTC2313-12 Applications Information Intermodulation Distortion (IMD) Full-Power and –3dB Input Linear Bandwidth If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.
PAGE 17
LTC2313-12 Applications Information In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feed-through from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a “Wait” state during conversion or by using three-state buffers to isolate the ADC data bus. Figure 16.
PAGE 18
LTC2313-12 Applications Information Figure 19. Layer 3 PWR Plane Figure 20. Layer 4 Bottom Layer 231312fa 18 For more information www.linear.
PAGE 19
LTC2313-12 Applications Information REF U5 LT1790ACS6-2.048 9V TO 10V 4 VI GND GND 1 2 JP1 HD1X3-100 J4 AIN 0V TO 4.096V C6 4.7µF R14 0k VO AC R9 1k C8 10µF VCCIO C9 4.7µF C10 OPT C11 OPT C12 4.7µF DC COUPLING 1 2 3 C18 OPT C7 OPT VDD VCM 6 + R15 49.9Ω C17 1µF 3 2 1 U1 * 4 C19 47pF NP0 JP2 VCM 1.024V 1 2 5 VDD REF OVDD AIN CSL SCK GND 3 SDO 231312 F21 8 CSL* 7 SCK SDO 6 R16 33Ω 2.048V HD1X3-100 R18 1k *CSL = CONV Figure 21.
PAGE 20
LTC2313-12 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 0.40 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 – 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.
PAGE 21
LTC2313-12 Revision History REV DATE DESCRIPTION A 11/13 Added pin-compatible family table PAGE NUMBER Reordered/renumbered notes 1 3, 5 231312fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. For more www.linear.
PAGE 22
LTC2313-12 Typical Application Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Re-Timing Flip-Flop VCC 0.1µF 50Ω 1k NC7SVU04P5X MASTER CLOCK VCC 1k PRE D > Q CONV CLR NL17SZ74 CONTROL LOGIC (FPGA, CPLD, DSP, ETC.