Datasheet

LTC2295
2295fa
16
APPLICATIO S I FOR ATIO
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Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2295 is 10Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (±10%) duty cycle. Each half cycle must have
at least 40ns for the ADC internal circuitry to have enough
settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The
input clock duty cycle can vary and the clock duty cycle
stabilizer will maintain a constant 50% internal duty cycle.
If the clock is turned off for a long period of time, the duty
cycle stabilizer circuit will require a hundred clock cycles
for the PLL to lock onto the input clock. To use the clock
duty cycle stabilizer, the MODE pin should be connected
to 1/3V
DD
or 2/3V
DD
using external resistors. The MODE
pin controls both Channel A and Channel B—the duty
cycle stabilizer is either on or off for both channels.
The lower limit of the LTC2295 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2295 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
DD
and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
Figure 9. Digital Output Buffer
2295 F9
OV
DD
V
DD
V
DD
0.1µF
43Ω
TYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
LTC2295
Table 1. Output Codes vs Input Voltage
A
IN
+
– A
IN
–
D13 – D0 D13 – D0
(2V RANGE) OF (OFFSET BINARY) (2’s COMPLEMENT)
>+1.000000V 1 11 1111 1111 1111 01 1111 1111 1111
+0.999878V 0 11 1111 1111 1111 01 1111 1111 1111
+0.999756V 0 11 1111 1111 1110 01 1111 1111 1110
+0.000122V 0 10 0000 0000 0001 00 0000 0000 0001
0.000000V 0 10 0000 0000 0000 00 0000 0000 0000
–0.000122V 0 01 1111 1111 1111 11 1111 1111 1111
–0.000244V 0 01 1111 1111 1110 11 1111 1111 1110
–0.999878V 0 00 0000 0000 0001 10 0000 0000 0001
–1.000000V 0 00 0000 0000 0000 10 0000 0000 0000
<–1.000000V 1 00 0000 0000 0000 10 0000 0000 0000