Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QFN 64

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9

LTC2295

1

2295fa

CODE

0

–2.0

INL ERROR (LSB)

–1.0

–0.5

0

2.0

1.0

4096

8192

2295 G02

–1.5

1.5

0.5

12288

16384

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

FEATURES

DESCRIPTIO

U

APPLICATIO S

U

TYPICAL APPLICATIO

U

■

Integrated Dual 14-Bit ADCs

■

Sample Rate: 10Msps

■

Single 3V Supply (2.7V to 3.4V)

■

Low Power: 120mW

■

74.4dB SNR

■

90dB SFDR

■

110dB Channel Isolation

■

Multiplexed or Separate Data Bus

■

Flexible Input: 1V

P-P

to 2V

P-P

Range

■

575MHz Full Power Bandwidth S/H

■

Clock Duty Cycle Stabilizer

■

Shutdown and Nap Modes

■

Pin Compatible Family

105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)

80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)

65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)

40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)

25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)

10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)

■

64-Pin (9mm × 9mm) QFN Package

Dual 14-Bit, 10Msps

Low Power 3V ADC

The LTC

®

2295 is a 14-bit 10Msps, low power dual 3V

A/D converter designed for digitizing high frequency, wide

dynamic range signals. The LTC2295 is perfect for

demanding imaging and communications applications

with AC performance that includes 74.4dB SNR and 90dB

SFDR for signals well beyond the Nyquist frequency.

DC specs include ±1.2LSB INL (typ), ±0.5LSB DNL (typ)

and no missing codes over temperature. The transition

noise is a low 1LSB

RMS

.

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.6V

logic. An optional multiplexer allows both channels to

share a digital output bus.

A single-ended CLK input controls converter operation. An

optional clock duty cycle stabilizer allows high perfor-

mance at full speed for a wide range of clock duty cycles.

■

Wireless and Wired Broadband Communication

■

Imaging Systems

■

Spectral Analysis

■

Portable Instrumentation

Typical INL, 2V Range

–

+

INPUT

S/H

ANALOG

INPUT A

ANALOG

INPUT B

CLK A

CLK B

14-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

OUTPUT

DRIVERS

•

•

•

OV

DD

OGND

MUX

D13A

D0A

•

•

•

OV

DD

OGND

2295 TA01

D13B

D0B

–

+

OUTPUT

DRIVERS

INPUT

S/H

14-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

Summary of content (24 pages)

PAGE 1
LTC2295 Dual 14-Bit, 10Msps Low Power 3V ADC U FEATURES DESCRIPTIO ■ The LTC®2295 is a 14-bit 10Msps, low power dual 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2295 is perfect for demanding imaging and communications applications with AC performance that includes 74.4dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Integrated Dual 14-Bit ADCs Sample Rate: 10Msps Single 3V Supply (2.7V to 3.
PAGE 2
LTC2295 U W U PACKAGE/ORDER I FOR ATIO U W W W ABSOLUTE AXI U RATI GS OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................
PAGE 3
LTC2295 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VIN Analog Input Range (AIN+ –AIN–) VIN,CM Analog Input Common Mode (AIN+ CONDITIONS +AIN –)/2 MIN 2.7V < VDD < 3.4V (Note 7) ● TYP MAX UNITS ±0.5 to ±1 V Differential Input (Note 7) ● 1 1.5 1.9 V Single Ended Input (Note 7) ● 0.5 1.
PAGE 4
LTC2295 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V ±25 VCM Output Tempco ppm/°C VCM Line Regulation 2.7V < VDD < 3.3V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 5
LTC2295 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) SYMBOL PARAMETER CONDITIONS MIN TYP MAX VDD Analog Supply Voltage (Note 9) OVDD Output Supply Voltage IVDD Supply Current PDISS UNITS ● 2.7 3 3.4 (Note 9) ● 0.5 3 3.
PAGE 6
LTC2295 U W TYPICAL PERFOR A CE CHARACTERISTICS Typical INL, 2V Range Crosstalk vs Input Frequency Typical DNL, 2V Range 1.0 2.0 –100 0.8 1.5 –105 0.6 –110 –115 –120 DNL ERROR (LSB) INL ERROR (LSB) CROSSTALK (dB) 1.0 0.5 0 –0.5 –1.0 –125 –130 0 20 40 60 80 INPUT FREQUENCY (MHz) –0.2 –0.4 –1.5 –0.8 –2.0 –1.
PAGE 7
LTC2295 U W TYPICAL PERFOR A CE CHARACTERISTICS SNR vs Input Level, fIN = 5MHz, 2V Range SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 80 100 120 dBFS 80 SNR 70 100 60 SFDR (dBc AND dBFS) SNR (dBc AND dBFS) 90 50 40 dBc 30 20 10 12 4 6 8 SAMPLE RATE (Msps) 14 dBc 80 70 60 100dBc SFDR REFERENCE LINE 50 40 30 10 0 –70 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 0 –80 –40 –20 –60 INPUT LEVEL (dBFS) 2295 G11 2295 G10 IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 0 22
PAGE 8
LTC2295 U U U PI FU CTIO S AINA+ (Pin 1): Channel A Positive Differential Analog Input. AINA– (Pin 2): Channel A Negative Differential Analog Input. REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFLA (Pins 5, 6): Channel A Low Reference.
PAGE 9
LTC2295 U U U PI FU CTIO S SHDNA (Pin 59): Channel A Shutdown Mode Selection Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting SHDNA to VDD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to VDD and OEA to VDD results in sleep mode with the outputs at high impedance.
PAGE 10
LTC2295 W UW TI I G DIAGRA S Dual Digital Output Bus Timing (Only One Channel is Shown) tAP N+4 N+2 N ANALOG INPUT N+1 tH N+3 N+5 tL CLK tD N–4 N–5 D0-D13, OF N–3 N–2 N–1 N 2295 TD01 Multiplexed Digital Output Bus Timing tAPA ANALOG INPUT A A+4 A+2 A A+1 A+3 tAPB ANALOG INPUT B B+4 B+2 B B+1 tH tL A–5 B–5 B+3 CLKA = CLKB = MUX D0A-D13A, OFA A–4 tD D0B-D13B, OFB B–5 B–4 A–3 B–3 A–2 B–2 B–3 A–3 B–2 A–2 A–1 t MD A–5 B–4 A–4 B–1 2295 TD02 2295fa 10
PAGE 11
LTC2295 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.
PAGE 12
LTC2295 U U W U APPLICATIO S I FOR ATIO applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2295 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier.
PAGE 13
LTC2295 U W U U APPLICATIO S I FOR ATIO high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small.
PAGE 14
LTC2295 U W U U APPLICATIO S I FOR ATIO Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT + AIN+ LTC2295 + CM – 2.2µF 12pF – 25Ω AIN– 2295 F04 Figure 4.
PAGE 15
LTC2295 U W U U APPLICATIO S I FOR ATIO The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 6. Each ADC channel has an independent reference with its own bypass capacitors.
PAGE 16
LTC2295 U W U U APPLICATIO S I FOR ATIO Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2295 is 10Msps. For the ADC to operate properly, the CLK signal should have a 50% (±10%) duty cycle. Each half cycle must have at least 40ns for the ADC internal circuitry to have enough settling time for proper operation. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle.
PAGE 17
LTC2295 U W U U APPLICATIO S I FOR ATIO As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2295 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF.
PAGE 18
LTC2295 U W U U APPLICATIO S I FOR ATIO Digital Output Multiplexer The digital outputs of the LTC2295 can be multiplexed onto a single data bus. The MUX pin is a digital input that swaps the two data busses. If MUX is High, Channel A comes out on DA0-DA13, OFA; Channel B comes out on DB0-DB13, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0-DB13, OFB; Channel B comes out on DA0-DA13, OFA.
PAGE 19
J3 CLOCK INPUT R14 49.9Ω C19 0.1µF VDD R15 1k R10 1k L1 BEAD VCMA C7 0.1µF J4 ANALOG R17 INPUT B OPT U6 NC7SVU04 VCM VDD 4 2 EXT REF 5 6 3 1 4 R8 51Ω R32 22Ω VCMB C33 0.1µF 5 • R23 51Ω •3 2 C29 T2 0.1µF ETC1-1T 4 1 R16 33Ω C17 0.1µF VDD R7 24.9Ω R6 24.9Ω R5 24.9Ω C6 12pF R24 24.9Ω C34 0.1µF R22 24.9Ω C31 12pF C23 1µF C20 2.2µF C18 1µF R20 24.9Ω 1/3VDD 2/3VDD VDD 6 4 2 VCMB VDD VCMB VDD C21 0.1µF C11 0.1µF C4 0.
PAGE 20
LTC2295 U W U U APPLICATIO S I FOR ATIO Silkscreen Top Top Side 2295fa 20
PAGE 21
LTC2295 U W U U APPLICATIO S I FOR ATIO Inner Layer 2 GND Inner Layer 3 Power 2295fa 21
PAGE 22
LTC2295 U W U U APPLICATIO S I FOR ATIO Bottom Side 2295fa 22
PAGE 23
LTC2295 U PACKAGE DESCRIPTIO UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ±0.05 7.15 ±0.05 8.10 ±0.05 9.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP 63 64 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER 7.15 ± 0.10 (4-SIDES) 0.25 ± 0.05 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2.
PAGE 24
LTC2295 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2221 12-Bit, 135Msps ADC 630mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2222 12-Bit, 105Msps ADC 475mW, 67.9dB SNR, 7mm × 7mm QFN Package LTC2223 12-Bit, 80Msps ADC 366mW, 68dB SNR, 7mm × 7mm QFN Package LTC2224 12-Bit, 135Msps ADC 630mW, 67.5dB SNR, 7mm × 7mm QFN Package LTC2225 12-Bit, 10Msps ADC 60mW, 71.