Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QFN 64

LTC2293/LTC2292/LTC2291

229321fa

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

INPUT FREQUENCY (MHz)

SNR (dBFS)

200

229321 TA02

100

150

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

■

Integrated Dual 12-Bit ADCs

■

Sample Rate: 65Msps/40Msps/25Msps

■

Single 3V Supply (2.7V to 3.4V)

■

Low Power: 400mW/235mW/150mW

■

71.3dB SNR

■

90dB SFDR

■

110dB Channel Isolation at 100MHz

■

Multiplexed or Separate Data Bus

■

Flexible Input: 1V

P-P

to 2V

P-P

Range

■

575MHz Full Power Bandwidth S/H

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Clock Duty Cycle Stabilizer

■

Shutdown and Nap Modes

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Pin Compatible Family

105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)

80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)

65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)

40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)

25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)

10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)

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64-Pin (9mm × 9mm) QFN Package

Dual 12-Bit, 65/40/25Msps

Low Power 3V ADCs

The LTC

2293/LTC2292/LTC2291 are 12-bit 65Msps/

40Msps/25Msps, low power dual 3V A/D converters de-

signed for digitizing high frequency, wide dynamic range

signals. The LTC2293/LTC2292/LTC2291 are perfect for

demanding imaging and communications applications

with AC performance that includes 71.3dB SNR and 90dB

SFDR for signals at the Nyquist frequency.

DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)

and no missing codes over temperature. The transition

noise is a low 0.25LSB

RMS

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.6V

logic. An optional multiplexer allows both channels to

share a digital output bus.

A single-ended CLK input controls converter operation. An

optional clock duty cycle stabilizer allows high perfor-

mance at full speed for a wide range of clock duty cycles.

LTC2293: SNR vs Input Frequency,

–1dB, 2V Range, 65Msps

–

INPUT

S/H

ANALOG

INPUT A

ANALOG

INPUT B

CLK A

CLK B

12-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

OUTPUT

DRIVERS

•

OGND

MUX

D11A

D0A

•

OGND

229321 TA01

D11B

D0B

–

OUTPUT

DRIVERS

INPUT

S/H

12-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

■

Wireless and Wired Broadband Communication

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Imaging Systems

■

Spectral Analysis

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Portable Instrumentation

Summary of content (28 pages)

PAGE 1
LTC2293/LTC2292/LTC2291 Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®2293/LTC2292/LTC2291 are 12-bit 65Msps/ 40Msps/25Msps, low power dual 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2293/LTC2292/LTC2291 are perfect for demanding imaging and communications applications with AC performance that includes 71.3dB SNR and 90dB SFDR for signals at the Nyquist frequency.
PAGE 2
LTC2293/LTC2292/LTC2291 W W U W ABSOLUTE AXI U RATI GS OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation............................................
PAGE 3
LTC2293/LTC2292/LTC2291 U U SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ –AIN–) 2.7V < VDD < 3.4V (Note 7) ● VIN,CM Analog Input Common Mode (AIN+ +AIN–)/2 A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN TYP MAX UNITS ±0.5 V to ±1V V Differential Input (Note 7) ● 1 1.5 1.9 V Single Ended Input (Note 7) ● 0.5 1.
PAGE 4
LTC2293/LTC2292/LTC2291 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V ±25 VCM Output Tempco ppm/°C VCM Line Regulation 2.7V < VDD < 3.3V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 5
LTC2293/LTC2292/LTC2291 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) MIN LTC2293 TYP MAX MIN LTC2292 TYP MAX MIN LTC2291 TYP MAX SYMBOL PARAMETER CONDITIONS UNITS VDD Analog Supply Voltage (Note 9) ● 2.7 3 3.4 2.7 3 3.4 2.7 3 3.4 V OVDD Output Supply Voltage (Note 9) ● 0.5 3 3.6 0.5 3 3.6 0.5 3 3.
PAGE 6
LTC2293/LTC2292/LTC2291 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2293/LTC2292/LTC2291: Crosstalk vs Input Frequency LTC2293: Typical INL, 2V Range, 65Msps INL ERROR (LSB) CROSSTALK (dB) –105 –110 –115 –120 –125 –130 0 20 100 40 60 80 INPUT FREQUENCY (MHz) 1.00 1.00 0.75 0.75 0.50 0.50 DNL ERROR (LSB) –100 LTC2293: Typical DNL, 2V Range, 65Msps 0.25 0 –0.25 0 –0.25 –0.50 –0.50 –0.75 –0.75 –1.00 –1.
PAGE 7
LTC2293/LTC2292/LTC2291 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2293: SNR vs Input Frequency, –1dB, 2V Range, 65Msps LTC2293: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2293: SFDR vs Input Frequency, –1dB, 2V Range, 65Msps 110 100 72 95 90 SFDR (dBFS) SNR (dBFS) SNR AND SFDR (dBFS) 100 71 70 85 80 75 69 SFDR 90 80 SNR 70 70 68 65 100 150 50 INPUT FREQUENCY (MHz) 0 60 50 100 200 150 INPUT FREQUENCY (MHz) 0 200 0 60 80 40 SAMPLE RATE (Msps) LTC2293: SFDR vs In
PAGE 8
LTC2293/LTC2292/LTC2291 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2292: Typical INL, 2V Range, 40Msps 0 1.00 0.75 0.50 0.50 DNL ERROR (LSB) 0.75 0.25 0 –0.25 –0.50 –10 –20 –30 AMPLITUDE (dB) 1.00 INL ERROR (LSB) LTC2292: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 40Msps LTC2292: Typical DNL, 2V Range, 40Msps 0.25 0 –0.25 –0.75 –1.00 –1.
PAGE 9
LTC2293/LTC2292/LTC2291 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2292: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2292: SFDR vs Input Frequency, –1dB, 2V Range, 40Msps LTC2292: SNR vs Input Level, fIN = 5MHz, 2V Range, 40Msps 110 100 80 dBFS 95 SFDR (dBFS) 85 80 75 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) 100 90 70 SFDR 90 80 SNR 60 50 dBc 40 30 20 70 70 10 65 60 50 100 200 150 INPUT FREQUENCY (MHz) 0 20 40 60 SAMPLE RATE (Msps) 0 0 –60 80 –50 – 40 –30 –20
PAGE 10
LTC2293/LTC2292/LTC2291 U W TYPICAL PERFOR A CE CHARACTERISTICS 0 0 –10 –10 –20 –20 –20 –30 –30 –30 –40 –50 –60 –70 –80 AMPLITUDE (dB) 0 –10 AMPLITUDE (dB) AMPLITUDE (dB) LTC2291: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 25Msps LTC2291: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 25Msps LTC2291: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 25Msps –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 0 2 4 6 8 FREQUENCY (MHz) 12
PAGE 11
LTC2293/LTC2292/LTC2291 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2291: SFDR vs Input Level, fIN = 5MHz, 2V Range, 25Msps LTC2291: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.
PAGE 12
LTC2293/LTC2292/LTC2291 U U U PI FU CTIO S MUX (Pin 21): Digital Output Multiplexer Control. If MUX is High, Channel A comes out on DA0-DA11, OFA; Channel B comes out on DB0-DB11, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0DB11, OFB; Channel B comes out on DA0-DA11, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together. SHDNB (Pin 22): Channel B Shutdown Mode Selection Pin.
PAGE 13
LTC2293/LTC2292/LTC2291 W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE 1.5V REFERENCE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D11 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 0.
PAGE 14
LTC2293/LTC2292/LTC2291 W UW TI I G DIAGRA S Dual Digital Output Bus Timing (Only One Channel is Shown) tAP N+4 N+2 N ANALOG INPUT N+1 tH N+3 N+5 tL CLK tD N–4 N–5 D0-D11, OF N–3 N–2 N–1 N 229321 TD01 Multiplexed Digital Output Bus Timing tAPA ANALOG INPUT A A+4 A+2 A A+1 A+3 tAPB ANALOG INPUT B B+4 B+2 B B+1 tH tL A–5 B–5 B+3 CLKA = CLKB = MUX D0A-D11A, OFA A–4 tD D0B-D11B, OFB B–5 B–4 A–3 B–3 A–2 B–2 B–3 A–3 B–2 A–2 A–1 t MD A–5 B–4 A–4 B–1 229321 TD02 229
PAGE 15
LTC2293/LTC2292/LTC2291 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.
PAGE 16
LTC2293/LTC2292/LTC2291 U U W U APPLICATIO S I FOR ATIO sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2293/LTC2292/ LTC2291 have two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier.
PAGE 17
LTC2293/LTC2292/LTC2291 U W U U APPLICATIO S I FOR ATIO capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.
PAGE 18
LTC2293/LTC2292/LTC2291 U W U U APPLICATIO S I FOR ATIO VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT + – 2.2µF AIN+ + CM VCM 2.2µF 0.1µF LTC2293 LTC2292 LTC2291 25Ω 25Ω 0.1µF AIN– AIN+ 0.1µF T1 12pF – 12Ω ANALOG INPUT LTC2293 LTC2292 LTC2291 8pF 25Ω 12Ω AIN– T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 229321 F04 229321 F06 Figure 4. Differential Drive with an Amplifier Figure 5 shows a single-ended input circuit.
PAGE 19
LTC2293/LTC2292/LTC2291 U W U U APPLICATIO S I FOR ATIO Reference Operation Figure 9 shows the LTC2293/LTC2292/LTC2291 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.
PAGE 20
LTC2293/LTC2292/LTC2291 U W U U APPLICATIO S I FOR ATIO CLEAN SUPPLY 4.7µF SINUSOIDAL CLOCK INPUT 0.1µF 1k 4.7µF FERRITE BEAD FERRITE BEAD 0.1µF 0.1µF 1k CLK 50Ω CLEAN SUPPLY LTC2293 LTC2292 LTC2291 LTC2293 LTC2292 LTC2291 CLK 100Ω NC7SVU04 229321 F12 229321 F11 Figure 11. Sinusoidal Single-Ended CLK Drive The noise performance of the LTC2293/LTC2292/LTC2291 can depend on the clock signal quality as much as on the analog input.
PAGE 21
LTC2293/LTC2292/LTC2291 U W U U APPLICATIO S I FOR ATIO Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2293/LTC2292/ LTC2291 is 65Msps (LTC2293), 40Msps (LTC2292), and 25Msps (LTC2291). For the ADC to operate properly, the CLK signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 7.3ns (LTC2293), 11.8ns (LTC2292), and 18.9ns (LTC2291) for the ADC internal circuitry to have enough settling time for proper operation.
PAGE 22
LTC2293/LTC2292/LTC2291 U W U U APPLICATIO S I FOR ATIO ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. Lower OVDD voltages will also help reduce interference from the digital outputs. Data Format Using the MODE pin, the LTC2293/LTC2292/LTC2291 parallel digital output can be selected for offset binary or 2’s complement format. Note that MODE controls both Channel A and Channel B. Connecting MODE to GND or 1/3VDD selects offset binary output format.
PAGE 23
LTC2293/LTC2292/LTC2291 U W U U APPLICATIO S I FOR ATIO Grounding and Bypassing The LTC2293/LTC2292/LTC2291 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.
PAGE 24
J3 CLOCK INPUT R14 49.9Ω C19 0.1µF VDD R15 1k R10 1k L1 BEAD VCMA C7 0.1µF J4 ANALOG R17 INPUT B OPT U6 NC7SVU04 VCM VDD 4 2 EXT REF 5 6 3 1 4 R8 51 R32 22Ω C17 0.1µF VDD R7 24.9Ω R6 24.9Ω R9 24.9Ω C8 0.1µF C14 0.1µF VDD VCMB C33 0.1µF 5 • R23 51 •3 2 C6 12pF R24 24.9Ω C34 0.1µF R22 24.9Ω C31 12pF C23 1µF VDD C21 0.1µF C11 0.1µF C4 0.1µF VCMB VDD VCMB 8 6 4 2 E2 EXT REF B VDD GND 1/3VDD 2/3VDD C20 2.2µF C18 1µF R20 24.9Ω 7 5 3 1 VDD C10 2.
PAGE 25
LTC2293/LTC2292/LTC2291 U W U U APPLICATIO S I FOR ATIO Silkscreen Top Top Side 229321fa 25
PAGE 26
LTC2293/LTC2292/LTC2291 U W U U APPLICATIO S I FOR ATIO Inner Layer 3 Power Inner Layer 2 GND Bottom Side 229321fa 26
PAGE 27
LTC2293/LTC2292/LTC2291 U PACKAGE DESCRIPTIO UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ±0.05 7.15 ±0.05 8.10 ±0.05 9.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP 63 64 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER 7.15 ± 0.10 (4-SIDES) 0.25 ± 0.05 0.200 REF 0.00 – 0.05 NOTE: 1.
PAGE 28
LTC2293/LTC2292/LTC2291 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1748 14-Bit, 80Msps 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT®1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain LT1994 Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver Low Distortion: –94dBc at 1MHz LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 150mW, 81.