Datasheet

LTC2290
17
2290fa
Data Format
Using the MODE pin, the LTC2290 parallel digital output
can be selected for offset binary or 2’s complement
format. Note that MODE controls both Channel A and
Channel B. Connecting MODE to GND or 1/3V
DD
selects
offset binary output format. Connecting MODE to
2/3V
DD
or V
DD
selects 2’s complement output format. An
external resistor divider can be used to set the 1/3V
DD
or
2/3V
DD
logic values. Table 2 shows the logic states for the
MODE pin.
APPLICATIO S I FOR ATIO
WUU
U
OV
DD
can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OV
DD
. The logic outputs will
swing between OGND and OV
DD
.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. Channels
A and B have independent output enable pins (OEA, OEB).
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to V
DD
and OE
to GND results in nap mode, which typically dissipates
30mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA, and
Channel B is controlled by SHDNB and OEB. The nap, sleep
and output enable modes of the two channels are completely
independent, so it is possible to have one channel operat-
ing while the other channel is in nap or sleep mode.
Table 2. MODE Pin Function
Clock Duty
MODE Pin Output Format Cycle Stabilizer
0 Offset Binary Off
1/3V
DD
Offset Binary On
2/3V
DD
2’s Complement On
V
DD
2’s Complement Off
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven. For
example, if the converter is driving a DSP powered by a 1.8V
supply, then OV
DD
should be tied to that same 1.8V supply.