Datasheet

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LTC2288/LTC2287/LTC2286

228876fa

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

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Integrated Dual 10-Bit ADCs

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Sample Rate: 65Msps/40Msps/25Msps

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Single 3V Supply (2.7V to 3.4V)

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Low Power: 400mW/235mW/150mW

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61.8dB SNR

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85dB SFDR

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110dB Channel Isolation at 100MHz

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Multiplexed or Separate Data Bus

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Flexible Input: 1V

P-P

to 2V

P-P

Range

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575MHz Full Power Bandwidth S/H

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Clock Duty Cycle Stabilizer

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Shutdown and Nap Modes

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Pin Compatible Family

105Msps: LTC2282 (12-Bit), LTC2280 (10-Bit)

80Msps: LTC2294 (12-Bit), LTC2289 (10-Bit)

65Msps: LTC2293 (12-Bit), LTC2288 (10-Bit)

40Msps: LTC2292 (12-Bit), LTC2287 (10-Bit)

25Msps: LTC2291 (12-Bit), LTC2286 (10-Bit)

10Msps: LTC2290 (12-Bit), LTC2292 (14-Bit)

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64-Pin (9mm × 9mm) QFN Package

Dual 10-Bit, 65/40/25Msps

Low Noise 3V ADCs

The LTC

2288/LTC2287/LTC2286 are 10-bit 65Msps/

40Msps/25Msps, low noise dual 3V A/D converters de-

signed for digitizing high frequency, wide dynamic range

signals. The LTC2288/LTC2287/LTC2286 are perfect for

demanding imaging and communications applications

with AC performance that includes 61.8dB SNR and 85dB

SFDR for signals at the Nyquist frequency.

DC specs include ±0.1LSB INL (typ), ±0.05LSB DNL (typ)

and ±0.6 LSB INL, ±0.5 LSB DNL over temperature. The

transition noise is a low 0.07LSB

RMS

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.6V

logic. An optional multiplexer allows both channels to

share one digital output bus.

A single-ended CLK input controls converter operation. An

optional clock duty cycle stabilizer allows high perfor-

mance at full speed for a wide range of clock duty cycles.

LTC2288: SNR vs Input Frequency,

–1dB, 2V Range, 65Msps

–

INPUT

S/H

ANALOG

INPUT A

ANALOG

INPUT B

CLK A

CLK B

10-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

OUTPUT

DRIVERS

•

OGND

MUX

D9A

D0A

•

OGND

228876 TA01

D9B

D0B

–

OUTPUT

DRIVERS

INPUT

S/H

10-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

INPUT FREQUENCY (MHz)

SNR (dBFS)

59.5

60.5

200

228876 TA02

58.5

57.5

100

150

62.5

61.5

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Wireless and Wired Broadband Communication

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Imaging Systems

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Spectral Analysis

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Portable Instrumentation

Summary of content (28 pages)

PAGE 1
LTC2288/LTC2287/LTC2286 Dual 10-Bit, 65/40/25Msps Low Noise 3V ADCs DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®2288/LTC2287/LTC2286 are 10-bit 65Msps/ 40Msps/25Msps, low noise dual 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2288/LTC2287/LTC2286 are perfect for demanding imaging and communications applications with AC performance that includes 61.8dB SNR and 85dB SFDR for signals at the Nyquist frequency.
PAGE 2
LTC2288/LTC2287/LTC2286 W W U W ABSOLUTE AXI U RATI GS OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................
PAGE 3
LTC2288/LTC2287/LTC2286 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ –AIN–) MIN 2.7V < VDD < 3.4V (Note 7) ● VIN,CM Analog Input Common Mode (AIN+ +AIN–)/2 TYP MAX UNITS ±0.5 to ±1 V Differential Input (Note 7) ● 1 1.5 1.9 V Single Ended Input (Note 7) ● 0.5 1.
PAGE 4
LTC2288/LTC2287/LTC2286 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V ±25 VCM Output Tempco ppm/°C VCM Line Regulation 2.7V < VDD < 3.3V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 5
LTC2288/LTC2287/LTC2286 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) MIN LTC2288 TYP MAX MIN LTC2287 TYP MAX MIN LTC2286 TYP MAX SYMBOL PARAMETER CONDITIONS UNITS VDD Analog Supply Voltage (Note 9) ● 2.7 3 3.4 2.7 3 3.4 2.7 3 3.4 V OVDD Output Supply Voltage (Note 9) ● 0.5 3 3.6 0.5 3 3.6 0.5 3 3.
PAGE 6
LTC2288/LTC2287/LTC2286 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2288: Typical INL, 2V Range, 65Msps LTC2288/LTC2287/LTC2286: Crosstalk vs Input Frequency INL ERROR (LSB) CROSSTALK (dB) –105 –110 –115 –120 –125 –130 1.00 1.00 0.75 0.75 0.50 0.50 0.25 0 –0.25 20 –0.25 –0.75 –0.75 –1.
PAGE 7
LTC2288/LTC2287/LTC2286 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2288: SNR vs Input Frequency, –1dB, 2V Range, 65Msps LTC2288: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2288: SFDR vs Input Frequency, –1dB, 2V Range, 65Msps 100 62.5 100 SFDR 95 90 SNR AND SFDR (dBFS) 61.5 SFDR (dBFS) 60.5 59.5 85 80 75 58.
PAGE 8
LTC2288/LTC2287/LTC2286 U W TYPICAL PERFOR A CE CHARACTERISTICS 1.00 0.75 0.75 0.50 0.50 0.25 0 –0.25 0 –0.25 –0.50 –0.75 –0.75 –1.00 –1.00 512 1024 768 –20 0.25 –0.50 256 0 –10 AMPLITUDE (dB) 1.
PAGE 9
LTC2288/LTC2287/LTC2286 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2287: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2287: SFDR vs Input Frequency, –1dB, 2V Range, 40Msps 100 LTC2287: SNR vs Input Level, fIN = 5MHz, 2V Range, 40Msps 100 80 SFDR 95 70 dBFS SFDR (dBFS) 90 85 80 75 60 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) 90 80 70 SNR 50 30 20 60 70 dBc 40 10 65 50 100 50 200 150 INPUT FREQUENCY (MHz) 0 0 10 20 30 40 50 60 SAMPLE RATE (Msps) 228876 G26 70 0 –60
PAGE 10
LTC2288/LTC2287/LTC2286 U W TYPICAL PERFOR A CE CHARACTERISTICS 0 0 0 –10 –10 –10 –20 –20 –30 –30 –40 –40 –40 –50 –60 –70 –80 AMPLITUDE (dB) –20 –30 AMPLITUDE (dB) AMPLITUDE (dB) LTC2286: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 25Msps LTC2286: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 25Msps LTC2286: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 25Msps –50 –60 –70 –80 –50 –60 –70 –80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 0 8 6 4 10 FREQUENCY (MHz) 2
PAGE 11
LTC2288/LTC2287/LTC2286 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2286: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.
PAGE 12
LTC2288/LTC2287/LTC2286 U U U PI FU CTIO S MUX (Pin 21): Digital Output Multiplexer Control. If MUX is High, Channel A comes out on DA0-DA9, OFA; Channel B comes out on DB0-DB9, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0DB9, OFB; Channel B comes out on DA0-DA9, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together. SHDNB (Pin 22): Channel B Shutdown Mode Selection Pin.
PAGE 13
LTC2288/LTC2287/LTC2286 W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE 1.5V REFERENCE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D9 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 0.
PAGE 14
LTC2288/LTC2287/LTC2286 W UW TI I G DIAGRA S Dual Digital Output Bus Timing (Only One Channel is Shown) tAP N+4 N+2 N ANALOG INPUT N+1 tH N+3 N+5 tL CLK tD N–4 N–5 D0-D9, OF N–3 N–2 N–1 N 228876 TD01 Multiplexed Digital Output Bus Timing tAPA ANALOG INPUT A A+4 A+2 A A+1 A+3 tAPB ANALOG INPUT B B+4 B+2 B B+1 tH tL A–5 B–5 B+3 CLKA = CLKB = MUX D0A-D9A, OFA A–4 tD D0B-D9B, OFB B–5 B–4 A–3 B–3 A–2 B–2 B–3 A–3 B–2 A–2 A–1 t MD A–5 B–4 A–4 B–1 228876 TD02 228876
PAGE 15
LTC2288/LTC2287/LTC2286 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.
PAGE 16
LTC2288/LTC2287/LTC2286 U U W U APPLICATIO S I FOR ATIO sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2288/LTC2287/ LTC2286 have two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier.
PAGE 17
LTC2288/LTC2287/LTC2286 U W U U APPLICATIO S I FOR ATIO capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.
PAGE 18
LTC2288/LTC2287/LTC2286 U W U U APPLICATIO S I FOR ATIO VCM VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT + – AIN+ + CM 2.2µF 2.2µF 0.1µF LTC2288 LTC2287 LTC2286 12Ω ANALOG INPUT 25Ω 25Ω 0.1µF T1 12pF – 0.1µF AIN– AIN+ LTC2288 LTC2287 LTC2286 8pF 25Ω 12Ω AIN– T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 228876 F04 228876 F06 Figure 4. Differential Drive with an Amplifier Figure 5 shows a single-ended input circuit.
PAGE 19
LTC2288/LTC2287/LTC2286 U W U U APPLICATIO S I FOR ATIO Reference Operation Figure 9 shows the LTC2288/LTC2287/LTC2286 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.
PAGE 20
LTC2288/LTC2287/LTC2286 U W U U APPLICATIO S I FOR ATIO CLEAN SUPPLY 4.7µF SINUSOIDAL CLOCK INPUT 0.1µF FERRITE BEAD FERRITE BEAD 0.1µF 0.1µF 1k CLK 50Ω 1k CLEAN SUPPLY 4.7µF LTC2288 LTC2287 LTC2286 LTC2288 LTC2287 LTC2286 CLK 100Ω NC7SVU04 228876 F12 228876 F11 Figure 11. Sinusoidal Single-Ended CLK Drive The noise performance of the LTC2288/LTC2287/LTC2286 can depend on the clock signal quality as much as on the analog input.
PAGE 21
LTC2288/LTC2287/LTC2286 U W U U APPLICATIO S I FOR ATIO An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle.
PAGE 22
LTC2288/LTC2287/LTC2286 U W U U APPLICATIO S I FOR ATIO Data Format Using the MODE pin, the LTC2288/LTC2287/LTC2286 parallel digital output can be selected for offset binary or 2’s complement format. Note that MODE controls both Channel A and Channel B. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values.
PAGE 23
LTC2288/LTC2287/LTC2286 U W U U APPLICATIO S I FOR ATIO Grounding and Bypassing The LTC2288/LTC2287/LTC2286 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.
PAGE 24
J3 CLOCK INPUT R14 49.9Ω C19 0.1µF VDD R15 1k R10 1k L1 BEAD VCMA C7 0.1µF J4 ANALOG R17 INPUT B OPT U6 NC7SVU04 VCM VDD 4 2 EXT REF 5 6 3 1 4 R8 51 R32 22Ω VCMB C33 0.1µF 5 • R23 51 •3 2 C29 T2 0.1µF ETC1-1T 4 1 R16 33Ω C17 0.1µF VDD R7 24.9Ω R6 24.9Ω R5 24.9Ω C6 12pF R24 24.9Ω C34 0.1µF R22 24.9Ω C31 12pF C23 1µF VDD C21 0.1µF C11 0.1µF C4 0.1µF VCMB VDD VCMB 8 6 4 2 E2 EXT REF B VDD GND 1/3VDD 2/3VDD C20 2.2µF C18 1µF R20 24.9Ω 7 5 3 1 C10 2.
PAGE 25
LTC2288/LTC2287/LTC2286 U W U U APPLICATIO S I FOR ATIO Silkscreen Top Top Side 228876fa 25
PAGE 26
LTC2288/LTC2287/LTC2286 U W U U APPLICATIO S I FOR ATIO Inner Layer 3 Power Inner Layer 2 GND Bottom Side 228876fa 26
PAGE 27
LTC2288/LTC2287/LTC2286 U PACKAGE DESCRIPTIO UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ±0.05 7.15 ±0.05 8.10 ±0.05 9.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP 63 64 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER 7.15 ± 0.10 (4-SIDES) 0.25 ± 0.05 0.200 REF 0.00 – 0.05 NOTE: 1.
PAGE 28
LTC2288/LTC2287/LTC2286 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1748 14-Bit, 80Msps 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT®1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain LT1994 Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver Low Distortion: –94dBc at 1MHz LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 150mW, 81.