Datasheet
LTC2284
9
2284fa
SHIFT REGISTER
AND CORRECTION
DIFF
REF
AMP
REF
BUF
2.2µF
1µF1µF
0.1µF
INTERNAL CLOCK SIGNALSREFH REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.5V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
REFH
REFL
CLK
OEMODE
OGND
OV
DD
2284 F01
INPUT
S/H
SENSE
V
CM
A
IN
–
A
IN
+
2.2µF
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
SHDN
OF
D13
D0
•
•
•
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to V
DD
results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNA to V
DD
and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to V
DD
and OEA to V
DD
results in sleep mode with the outputs at
high impedance.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects offset binary
output format and turns the clock duty cycle stabilizer off.
1/3 V
DD
selects offset binary output format and turns the
clock duty cycle stabilizer on. 2/3 V
DD
selects 2’s comple-
ment output format and turns the clock duty cycle
UU
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PI FU CTIO S
stabilizer on. V
DD
selects 2’s complement output format
and turns the clock duty cycle stabilizer off.
V
CMA
(Pin 61): Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to V
CMB
.
SENSEA (Pin 62): Channel A Reference Programming Pin.
Connecting SENSEA to V
CMA
selects the internal reference
and a ±0.5V input range. V
DD
selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of ±V
SENSEA
. ±1V is the largest valid input range.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
FUNCTIONAL BLOCK DIAGRA
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Figure 1. Functional Block Diagram (Only One Channel is Shown)