Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QFN 64

LTC2284

2284fa

INPUT FREQUENCY (MHz)

SNR (dBFS)

100

200

250

2284 TA01b

150

300

350

–

INPUT

S/H

ANALOG

INPUT A

ANALOG

INPUT B

CLK A

CLK B

14-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

OUTPUT

DRIVERS

•

OGND

MUX

D13A

D0A

•

OGND

2284 TA01

D13B

D0B

–

OUTPUT

DRIVERS

INPUT

S/H

14-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

■

Integrated Dual 14-Bit ADCs

■

Sample Rate: 105Msps

■

Single 3V Supply (2.85V to 3.4V)

■

Low Power: 540mW

■

72.4dB SNR, 88dB SFDR

■

110dB Channel Isolation at 100MHz

■

Flexible Input: 1V

P-P

to 2V

P-P

Range

■

575MHz Full Power Bandwidth S/H

■

Clock Duty Cycle Stabilizer

■

Shutdown and Nap Modes

■

Pin Compatible Family

105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)

80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)

65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)

40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)

25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)

10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)

■

64-Pin (9mm × 9mm) QFN Package

Dual 14-Bit, 105Msps

Low Power 3V ADC

The LTC

2284 is a 14-bit 105Msps, low power dual 3V

A/D converter designed for digitizing high frequency, wide

dynamic range signals. The LTC2284 is perfect for

demanding imaging and communications applications

with AC performance that includes 72.4dB SNR and 85dB

SFDR for signals at the Nyquist frequency.

Typical DC specs include ±1.5LSB INL, ±0.6LSB DNL. The

transition noise is a low 1.3LSB

RMS

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.6V

logic.

A single-ended CLK input controls converter operation. An

optional clock duty cycle stabilizer allows high perfor-

mance at full speed for a wide range of clock duty cycles.

SNR vs Input Frequency,

–1dB, 2V Range

■

Wireless and Wired Broadband Communication

■

Imaging Systems

■

Spectral Analysis

■

Portable Instrumentation

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Summary of content (24 pages)

PAGE 1
LTC2284 Dual 14-Bit, 105Msps Low Power 3V ADC U FEATURES DESCRIPTIO ■ The LTC®2284 is a 14-bit 105Msps, low power dual 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2284 is perfect for demanding imaging and communications applications with AC performance that includes 72.4dB SNR and 85dB SFDR for signals at the Nyquist frequency. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Integrated Dual 14-Bit ADCs Sample Rate: 105Msps Single 3V Supply (2.85V to 3.4V) Low Power: 540mW 72.
PAGE 2
LTC2284 U W U PACKAGE/ORDER I FOR ATIO U W W W ABSOLUTE AXI U RATI GS OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................
PAGE 3
LTC2284 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ –AIN–) 2.85V < VDD < 3.4V (Note 7) ● VIN,CM Analog Input Common Mode (AIN+ +AIN–)/2 Differential Input Drive (Note 7) Single Ended Input Drive (Note 7) ● ● 1 0.
PAGE 4
LTC2284 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V ±25 VCM Output Tempco ppm/°C VCM Line Regulation 2.85V < VDD < 3.4V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 5
LTC2284 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Analog Supply Voltage (Note 9) ● 2.85 3 3.4 V OVDD Output Supply Voltage (Note 9) ● 0.5 3 3.
PAGE 6
LTC2284 U W TYPICAL PERFOR A CE CHARACTERISTICS Crosstalk vs Input Frequency Typical DNL, 2V Range, 105Msps Typical INL, 2V Range, 105Msps –100 –105 2.0 1.0 1.5 0.8 0.6 –110 –115 –120 0.4 DNL ERROR (LSB) INL ERROR (LSB) CROSSTALK (dB) 1.0 0.5 0 –0.5 0.2 0 –0.2 –0.4 –1.0 –125 –0.6 –1.5 –0.8 –1.0 –2.
PAGE 7
LTC2284 U W TYPICAL PERFOR A CE CHARACTERISTICS SNR vs Input Frequency, –1dB, 2V Range, 105Msps SFDR vs Input Frequency, –1dB, 2V Range, 105Msps SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 100 75 74 90 SFDR 95 90 SFDR (dBRS) 72 SNR (dBFS) SNR AND SFDR (dBFS) 73 71 70 69 68 85 80 75 67 SNR 70 60 70 66 65 65 0 50 0 100 150 200 250 300 350 2284 G25 INPUT FREQUENCY (MHz) SNR vs Input Level, fIN = 70MHz, 2V Range, 105Msps 80 50 50 100 150 200 250 300 350 2284 G26 INPUT FREQ
PAGE 8
LTC2284 U U U PI FU CTIO S AINA+ (Pin 1): Channel A Positive Differential Analog Input. AINA– (Pin 2): Channel A Negative Differential Analog Input. REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFLA (Pins 5, 6): Channel A Low Reference.
PAGE 9
LTC2284 U U U PI FU CTIO S SHDNA (Pin 59): Channel A Shutdown Mode Selection Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting SHDNA to VDD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to VDD and OEA to VDD results in sleep mode with the outputs at high impedance.
PAGE 10
LTC2284 W UW TI I G DIAGRA S Dual Digital Output Bus Timing (Only One Channel is Shown) tAP ANALOG INPUT N+4 N+2 N N+1 tH N+3 N+5 tL CLK tD N–4 N–5 D0-D13, OF N–3 N–2 N–1 N 2284 TD01 Multiplexed Digital Output Bus Timing tAPA ANALOG INPUT A A+4 A+2 A A+1 A+3 tAPB ANALOG INPUT B B+4 B+2 B B+1 tH tL A–5 B–5 B+3 CLKA = CLKB = MUX D0A-D13A, OFA A–4 tD D0B-D13B, OFB B–5 B–4 A–3 B–3 A–2 B–2 B–3 A–3 B–2 A–2 A–1 t MD A–5 B–4 A–4 B–1 2284 TD02 2284fa 10
PAGE 11
LTC2284 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.
PAGE 12
LTC2284 U U W U APPLICATIO S I FOR ATIO applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2284 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier.
PAGE 13
LTC2284 U W U U APPLICATIO S I FOR ATIO high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small.
PAGE 14
LTC2284 U W U U APPLICATIO S I FOR ATIO VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT + 2.2µF AIN+ 2.2µF 0.1µF LTC2284 12Ω ANALOG INPUT 25Ω + CM – VCM 25Ω 0.1µF AIN– LTC2284 0.1µF T1 12pF – AIN+ 8pF 25Ω 12Ω AIN– T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 2284 F04 2284 F06 Figure 4. Differential Drive with an Amplifier Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched.
PAGE 15
LTC2284 U W U U APPLICATIO S I FOR ATIO Reference Operation Figure 9 shows the LTC2284 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.
PAGE 16
LTC2284 U W U U APPLICATIO S I FOR ATIO CLEAN SUPPLY 4.7µF CLEAN SUPPLY 4.7µF FERRITE BEAD FERRITE BEAD 0.1µF SINUSOIDAL CLOCK INPUT 0.1µF 1k CLK 50Ω 1k 0.1µF LTC2284 CLK LTC2284 100Ω NC7SVU04 2284 F11 2284 F12 Figure 11. Sinusoidal Single-Ended CLK Drive The noise performance of the LTC2284 can depend on the clock signal quality as much as on the analog input.
PAGE 17
LTC2284 U W U U APPLICATIO S I FOR ATIO architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2284 is 1Msps. Clock Duty Cycle Stabilizer An optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. Using the clock duty cycle stabilizer is recommended for most applications.
PAGE 18
LTC2284 U W U U APPLICATIO S I FOR ATIO Data Format Sleep and Nap Modes Using the MODE pin, the LTC2284 parallel digital output can be selected for offset binary or 2’s complement format. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3V DD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the MODE pin.
PAGE 19
LTC2284 U W U U APPLICATIO S I FOR ATIO Grounding and Bypassing The LTC2284 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.
PAGE 20
R14 49.9Ω C19 0.1µF 2 5 R10 1k ASSEMBLY TYPE DC851A-S DC851A-T 2 5 4 2 4 5 1 2 R8 51 •3 VDD 5 4 R7 24.9Ω • E5 PWR GND E3 VDD 3V C6, C31 12pF 8pF VDD E2 EXT REF B VCMB VDD VCM VDD 4 2 INPUT FREQUENCY fIN < 70MHz fIN > 70MHz C48 0.1µF EXT REF 5 6 3 1 C2 2.2µF C27 0.1µF JP3 SENSE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AINA+ AINA– REFHA REFHA REFLA REFLA VDD CLKA CLKB VDD REFLB REFLB REFHB REFHB AINB– AINB+ C1 0.1µF VDD C47 0.1µF C21 0.1µF C11 0.1µF C4 0.
PAGE 21
LTC2284 U W U U APPLICATIO S I FOR ATIO Silkscreen Top Top Side 2284fa 21
PAGE 22
LTC2284 U W U U APPLICATIO S I FOR ATIO Inner Layer 3 Power Inner Layer 2 GND Bottom Side 2284fa 22
PAGE 23
LTC2284 U PACKAGE DESCRIPTIO UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ±0.05 7.15 ±0.05 8.10 ±0.05 9.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP 63 64 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER 7.15 ± 0.10 (4-SIDES) 0.25 ± 0.05 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2.
PAGE 24
LTC2284 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2221 12-Bit, 135Msps ADC 630mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2222 12-Bit, 105Msps ADC 475mW, 67.9dB SNR, 7mm × 7mm QFN Package LTC2223 12-Bit, 80Msps ADC 366mW, 68dB SNR, 7mm × 7mm QFN Package LTC2224 12-Bit, 135Msps ADC 630mW, 67.5dB SNR, 7mm × 7mm QFN Package LTC2225 12-Bit, 10Msps ADC 60mW, 71.