Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QFN 64

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LTC2282

1

2282fb

TYPICAL APPLICATION

DESCRIPTION

Dual 12-Bit, 105Msps

Low Power 3V ADC

The LTC

®

2282 is a 12-bit 105Msps, low power dual 3V

A/D converter designed for digitizing high frequency,

wide dynamic range signals. The LTC2282 is perfect for

demanding imaging and communications applications

with AC performance that includes 70.1dB SNR and 85dB

SFDR for signals at the Nyquist frequency.

DC specs include ±0.4LSB INL (typ), ±0.2LSB DNL (typ)

and no missing codes over temperature. The transition

noise is a low 0.3LSB

RMS

.

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.6V

logic.

A single-ended CLK input controls converter operation. An

optional clock duty cycle stabilizer allows high performance

at full speed for a wide range of clock duty cycles.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

FEATURES

APPLICATIONS

n

Integrated Dual 12-Bit ADCs

n

Sample Rate: 105Msps

n

Single 3V Supply (2.85V to 3.4V)

n

Low Power: 540mW

n

70.1dB SNR, 88dB SFDR

n

110dB Channel Isolation at 100MHz

n

Flexible Input: 1V

P-P

to 2V

P-P

Range

n

575MHz Full Power Bandwidth S/H

n

Clock Duty Cycle Stabilizer

n

Shutdown and Nap Modes

n

Pin Compatible Family

105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)

80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)

65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)

40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)

25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)

10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)

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64-Pin (9mm × 9mm) QFN Package

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Wireless and Wired Broadband Communication

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Imaging Systems

n

Spectral Analysis

n

Portable Instrumentation

INPUT FREQUENCY (MHz)

0

SNR (dBFS)

72

150

2282 TA01b

69

67

50 100 200

66

65

73

71

70

68

250 300 350

–

+

INPUT

S/H

ANALOG

INPUT A

ANALOG

INPUT B

CLK A

CLK B

12-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

OUTPUT

DRIVERS

•

•

•

OV

DD

OGND

MUX

D11A

D0A

•

•

•

OV

DD

OGND

2282 TA01

D11B

D0B

–

+

OUTPUT

DRIVERS

INPUT

S/H

12-BIT

PIPELINED

ADC CORE

CLOCK/DUTY CYCLE

CONTROL

SNR vs Input Frequency,

–1dB, 2V Range

Summary of content (24 pages)

PAGE 1
LTC2282 Dual 12-Bit, 105Msps Low Power 3V ADC FEATURES DESCRIPTION n The LTC®2282 is a 12-bit 105Msps, low power dual 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2282 is perfect for demanding imaging and communications applications with AC performance that includes 70.1dB SNR and 85dB SFDR for signals at the Nyquist frequency. n n n n n n n n n n n Integrated Dual 12-Bit ADCs Sample Rate: 105Msps Single 3V Supply (2.85V to 3.4V) Low Power: 540mW 70.
PAGE 2
LTC2282 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION OVDD = VDD (Notes 1, 2) 64 GND 63 VDD 62 SENSEA 61 VCMA 60 MODE 59 SHDNA 58 OEA 57 OFA 56 DA11 55 DA10 54 DA9 53 DA8 52 DA7 51 DA6 50 OGND 49 OVDD TOP VIEW Supply Voltage (VDD) ..................................................4V Digital Output Ground Voltage (OGND) ........ –0.3V to 1V Analog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V) Digital Input Voltage......................–0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.
PAGE 3
LTC2282 CONVERTER CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 4) PARAMETER CONDITIONS Full-Scale Drift Internal Reference Gain Matching MIN TYP UNITS ±30 ppm/°C External Reference ±5 ppm/°C External Reference ±0.3 %FS ±2 mV 0.
PAGE 4
LTC2282 INTERNAL REFERENCE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX VCM Output Voltage IOUT = 0 1.475 1.500 1.525 VCM Output Tempco ±25 UNITS V ppm/°C VCM Line Regulation 2.85V < VDD < 3.4V 3 mV/ V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C.
PAGE 5
LTC2282 POWER REQUIREMENTS The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 8) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Analog Supply Voltage (Note 9) l 2.85 3 3.4 OVDD Output Supply Voltage IVDD Supply Current (Note 9) l 0.5 3 3.
PAGE 6
LTC2282 TYPICAL PERFORMANCE CHARACTERISTICS Crosstalk vs Input Frequency Typical INL, 2V Range, 105Msps INL ERROR (LSB) –110 –115 –120 –125 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0 –0.2 –0.4 0 –0.2 –0.4 –0.6 –0.6 –0.8 –0.8 20 40 60 80 INPUT FREQUENCY (MHz) 100 –1.
PAGE 7
LTC2282 TYPICAL PERFORMANCE CHARACTERISTICS SNR vs Input Frequency, –1dB, 2V Range, 105Msps SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB SFDR vs Input Frequency, –1dB, 2V Range, 105Msps 73 95 90 SFDR 72 90 69 68 SNR AND SFDR (dBFS) 70 SFDR (dBFS) SNR (dBFS) 71 85 80 75 67 SNR 70 60 70 66 65 50 65 150 200 250 300 350 2282 G25 INPUT FREQUENCY (MHz) 100 0 SNR vs Input Level, fIN = 70MHz, 2V Range, 105Msps 50 50 100 150 200 250 300 350 2282 G26 INPUT FREQUENCY (MHz) 0 SFDR
PAGE 8
LTC2282 PIN FUNCTIONS AINA+ (Pin 1): Channel A Positive Differential Analog Input. AINA– (Pin 2): Channel A Negative Differential Analog Input. REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.2μF ceramic chip capacitor and to ground with a 1μF ceramic chip capacitor. REFLA (Pins 5, 6): Channel A Low Reference. Short together and bypass to Pins 3, 4 with a 0.
PAGE 9
LTC2282 PIN FUNCTIONS SHDNA (Pin 59): Channel A Shutdown Mode Selection Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting SHDNA to VDD and OEA to GND results in nap mode with the outputs at high impedance. Connecting SHDNA to VDD and OEA to VDD results in sleep mode with the outputs at high impedance.
PAGE 10
LTC2282 TIMING DIAGRAMS Dual Digital Output Bus Timing (Only One Channel is Shown) tAP ANALOG INPUT N+4 N+2 N N+1 tH N+3 N+5 tL CLK tD N–4 N–5 D0-D11, OF N–3 N–2 N–1 N 2282 TD01 Multiplexed Digital Output Bus Timing tAPA ANALOG INPUT A A+4 A+2 A A+1 A+3 tAPB ANALOG INPUT B B+4 B+2 B B+1 tH tL A–5 B–5 B+3 CLKA = CLKB = MUX D0A-D11A, OFA A–4 tD D0B-D11B, OFB B–5 B–4 A–3 B–3 A–2 B–2 B–3 A–3 B–2 A–2 A–1 tMD A–5 B–4 A–4 B–1 2282 TD02 2282fb 10
PAGE 11
LTC2282 APPLICATIONS INFORMATION DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.
PAGE 12
LTC2282 APPLICATIONS INFORMATION analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2282 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue ampliﬁer. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue.
PAGE 13
LTC2282 APPLICATIONS INFORMATION acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.
PAGE 14
LTC2282 APPLICATIONS INFORMATION VCM VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT + AIN+ 0.1μF LTC2282 12Ω ANALOG INPUT 25Ω + CM – 2.2μF 2.2μF 25Ω 0.1μF AIN– LTC2282 0.1μF T1 12pF – AIN+ 8pF 25Ω 12Ω AIN– T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 2282 F04 2282 F06 Figure 4. Differential Drive with an Ampliﬁer Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched.
PAGE 15
LTC2282 APPLICATIONS INFORMATION Reference Operation Figure 9 shows the LTC2282 reference circuitry consisting of a 1.5V bandgap reference, a difference ampliﬁer and switching and control circuit. The internal voltage reference can be conﬁgured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.
PAGE 16
LTC2282 APPLICATIONS INFORMATION CLEAN SUPPLY 4.7μF SINUSOIDAL CLOCK INPUT FERRITE BEAD FERRITE BEAD 0.1μF 0.1μF 1k 0.1μF CLK 50Ω 1k CLEAN SUPPLY 4.7μF CLK LTC2282 100Ω LTC2282 NC7SVU04 IF LVDS, USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR 2282 F12 2282 F11 Figure 11. Sinusoidal Single-Ended CLK Drive Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter The noise performance of the LTC2282 can depend on the clock signal quality as much as on the analog input.
PAGE 17
LTC2282 APPLICATIONS INFORMATION signals on small valued capacitors. Junction leakage will discharge the capacitors. The speciﬁed minimum operating frequency for the LTC2282 is 1Msps. Clock Duty Cycle Stabilizer An optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. Using the clock duty cycle stabilizer is recommended for most applications.
PAGE 18
LTC2282 APPLICATIONS INFORMATION Table 2. MODE Pin Function Output Format Clock Duty Cycle Stabilizer 0 Offset Binary Off 1/3VDD Offset Binary On 2/3VDD 2’s Complement On VDD 2’s Complement Off MODE Pin Overﬂow Bit When OF outputs a logic high the converter is either overranged or underranged. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry.
PAGE 19
LTC2282 APPLICATIONS INFORMATION High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the 0.1μF capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402 ceramic capacitor is recommended. The large 2.2μF capacitor between REFH and REFL can be somewhat further away.
PAGE 20
R14 49.9Ω C19 0.1μF 5 ASSEMBLY TYPE DC851A-U DC851A-V 2 U1 LTC2282IUP LTC2282IUP + 4 2 2 1 R8 51 •3 VDD 5 4 • R9 * R7 24.9Ω 2 1 E5 PWR GND E3 VDD 3V C34 0.1μF GND VCMB VDD VCC AINA+ AINA– REFHA REFHA REFLA REFLA VDD CLKA CLKB VDD REFLB REFLB REFHB REFHB AINB– AINB+ VCM VDD 4 2 C47 0.1μF C48 0.1μF EXT REF 5 6 3 1 C2 2.2μF C27 0.1μF JP3 SENSE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD C1 0.1μF INPUT FREQUENCY fIN < 70MHz fIN > 70MHz C41 0.1μF VDD C21 0.
PAGE 21
LTC2282 APPLICATIONS INFORMATION Silkscreen Top Top Side 2282fb 21
PAGE 22
LTC2282 APPLICATIONS INFORMATION Inner Layer 2 GND Inner Layer 3 Power Bottom Side 2282fb 22
PAGE 23
LTC2282 PACKAGE DESCRIPTION UP Package 64-Lead Plastic QFN (9mm × 9mm) (Reference LTC DWG # 05-08-1705) 0.70 ±0.05 7.15 ±0.05 8.10 ±0.05 9.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 9 .00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.115 TYP 63 64 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER 7.15 ± 0.10 (4-SIDES) (UP64) QFN 1003 0.25 ± 0.05 0.200 REF 0.00 – 0.05 NOTE: 1.
PAGE 24
LTC2282 RELATED PARTS PART NUMBER DESCRIPTION LTC2220 12-Bit, 170Msps ADC COMMENTS 890mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2221 12-Bit, 135Msps ADC 630mW, 67.5dB SNR, 9mm × 9mm QFN Package LTC2222 12-Bit, 105Msps ADC 475mW, 67.9dB SNR, 7mm × 7mm QFN Package LTC2223 12-Bit, 80Msps ADC 366mW, 68dB SNR, 7mm × 7mm QFN Package 630mW, 67.5dB SNR, 7mm × 7mm QFN Package LTC2224 12-Bit, 135Msps ADC LTC2225 12-Bit, 10Msps ADC 60mW, 71.