Datasheet

LTC2268-14/
LTC2267-14/LTC2266-14
17
22687614fa
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the V
DD
of the part and not be driven
by a logic signal.
V
REF
(Pin 36): Reference Voltage Output. Bypass to ground
with a 1µF ceramic capacitor, nominally 1.25V.
SENSE (Pin 38): Reference Programming Pin. Connecting
SENSE to V
DD
selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • V
SENSE
.
LVDS Outputs
All pins below are differential LVDS outputs. The output
current level is programmable. There is an optional
internal 100Ω termination resistor between the pins of
each LVDS output pair.
OUT2B
–
/OUT2B
+
, OUT2A
–
/OUT2A
+
(Pins 19/20, 21/22):
Serial Data Outputs for Channel 2. In 1-lane output mode
only OUT2A
–
/OUT2A
+
are used.
FR
–
/FR
+
(Pins 23/24): Frame Start Outputs.
DCO
–
/DCO
+
(Pins 27/28): Data Clock Outputs.
OUT1B
–
/OUT1B
+
, OUT1A
–
/OUT1A
+
(Pins 29/30, 31/32):
Serial Data Outputs for Channel 1. In 1-lane output mode
only OUT1A
–
/OUT1A
+
are used.
pin FuncTions