Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QFN 40

LTC2268-14/

LTC2267-14/LTC2266-14

22687614fa

Typical applicaTion

DescripTion

14-Bit, 125Msps/105Msps/

80Msps Low Power Dual ADCs

The LTC

2268-14/LTC2267-14/LTC2266-14 are 2-channel,

simultaneous sampling 14-bit A/D converters designed

for digitizing high frequency, wide dynamic range signals.

They are perfect for demanding communications applica-

tions with AC performance that includes 73.1dB SNR and

88dB spurious free dynamic range (SFDR). Ultralow jitter

of 0.15ps

RMS

allows undersampling of IF frequencies with

excellent noise performance.

DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ)

and no missing codes over temperature. The transition

noise is a low 1.2LSB

RMS

The digital outputs are serial LVDS to minimize the num-

ber of data lines. Each channel outputs two bits at a time

(2-lane mode). At lower sampling rates there is a one bit

per channel option (1-lane mode). The LVDS drivers have

optional internal termination and adjustable output levels

to ensure clean signal integrity.

The ENC

and ENC

–

inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL, or

CMOS inputs. An internal clock duty cycle stabilizer al-

lows high performance at full speed for a wide range of

clock duty cycles.

FeaTures

applicaTions

2-Channel Simultaneous Sampling ADC

73.1dB SNR

88dB SFDR

Low Power: 299mW/243mW/203mW Total

150mW/121mW/101mW Per Channel

Single 1.8V Supply

Serial LVDS Outputs: 1 or 2 Bits Per Channel

Selectable Input Ranges: 1V

P-P

to 2V

P-P

800MHz Full Power Bandwidth S/H

Shutdown and Nap Modes

Serial SPI Port for Conﬁguration

Pin Compatible 14-Bit and 12-Bit Versions

40-Pin (6mm × 6mm) QFN Package

Communications

Cellular Base Stations

Software Deﬁned Radios

Portable Medical Imaging

Multichannel Data Acquisition

Nondestructive Testing

LTC2268-14, 125Msps,

2-Tone FFT, f

= 70MHz and 75MHz

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

CH.1

ANALOG

INPUT

CH.2

ANALOG

INPUT

ENCODE

INPUT

226814 TA01

GND OGND

14-BIT

ADC CORE

14-BIT

ADC CORE

PLL

DATA

SERIALIZER

SERIALIZED

LVDS

OUTPUTS

1.8V 1.8V

OUT1A

OUT1B

OUT2A

OUT2B

DATA

CLOCK

OUT

FRAME

S/H

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

20 30 40 50 60

226814 TA01b

Summary of content (32 pages)

PAGE 1
LTC2268-14/ LTC2267-14/LTC2266-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Dual ADCs Features n n n n n n n n n n n n n Description 2-Channel Simultaneous Sampling ADC 73.1dB SNR 88dB SFDR Low Power: 299mW/243mW/203mW Total 150mW/121mW/101mW Per Channel Single 1.
PAGE 2
LTC2268-14/ LTC2267-14/LTC2266-14 Absolute Maximum Ratings Pin Configuration (Note 1) OUT1A– OUT1A+ GND SDO PAR/SER VREF GND SENSE VDD TOP VIEW VDD Supply Voltages VDD, OVDD................................................. –0.3V to 2V Analog Input Voltage (AIN+, AIN–, PAR/SER, SENSE) (Note 3)..............–0.3V to (VDD+0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4)..................................... –0.3V to 3.9V SDO (Note 4)............................................. –0.
PAGE 3
LTC2268-14/ LTC2267-14/LTC2266-14 converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2268-14 PARAMETER CONDITIONS Resolution (No Missing Codes) MIN l 14 TYP LTC2267-14 MAX MIN TYP LTC2266-14 MAX MIN 14 TYP MAX UNITS 14 Bits Integral Linearity Error Differential Analog Input (Note 6) l –3.5 ±1 3.5 –3.5 ±1 3.5 –2.75 ±1 2.
PAGE 4
LTC2268-14/ LTC2267-14/LTC2266-14 digital accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) LTC2268-14 SYMBOL PARAMETER CONDITIONS SNR 5MHz Input 70MHz Input 140MHz Input Spurious Free Dynamic Range 2nd or 3rd Harmonic SFDR S/(N+D) LTC2267-14 MIN TYP MIN TYP MIN TYP l 71.4 73.1 73 72.6 70.8 73 72.9 72.6 71 73 72.9 72.
PAGE 5
LTC2268-14/ LTC2267-14/LTC2266-14 digital inputs and outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD =1.8V l VIL Low Level Input Voltage VDD =1.8V l IIN Input Current VIN = 0V to 3.
PAGE 6
LTC2268-14/ LTC2267-14/LTC2266-14 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 7
LTC2268-14/ LTC2267-14/LTC2266-14 TIMING Diagrams 2-Lane Output Mode, 16-Bit Serialization* tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tDATA tFRAME FR– FR+ tSER tPD tSER – OUT#A OUT#A+ OUT#B– OUT#B+ D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 226814 TD01 *SEE THE DIGITAL OUTPUTS SECTION 2-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+2 N+1 N tENC
PAGE 8
LTC2268-14/ LTC2267-14/LTC2266-14 TIMING Diagrams 2-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tDATA tFRAME FR+ FR– tPD tSER – OUT#A OUT#A+ OUT#B– OUT#B+ tSER D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 226814 TD03 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME FR– F
PAGE 9
LTC2268-14/ LTC2267-14/LTC2266-14 TIMING Diagrams 1-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ tDATA tSER tPD D3 D2 D1 tSER D0 SAMPLE N-6 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SAMPLE N-5 D13 D12 D11 D10 SAMPLE N-4 226814 TD05 OUT#B+, OUT#B– ARE DISABLED 1-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#
PAGE 10
LTC2268-14/ LTC2267-14/LTC2266-14 TIMING Diagrams SPI Port Timing (Readback Mode) CS tS tDS tDH tSCK tH tS tDS tDH tSCK tH SCK CS SCK SDI tDO R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX D7 XX XXD6 D5 XX D4 XX XXD3 D2 XX D1 XX XX D7 D6 D5 D4 D3 D2 D1 tDO SDO SDI SDO A6 R/W HIGH IMPEDANCE A5 A4 A3 A2 A1 A0 HIGH IMPEDANCE D0 D0 SPI Port Timing (Write Mode) CS SCK CS SCK SDI SDO SDI SDO A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 A6 R/
PAGE 11
LTC2268-14/ LTC2267-14/LTC2266-14 Typical Performance Characteristics LTC2268-14: Integral Nonlinearity (INL) LTC2268-14: Differential Nonlinearity (DNL) 2.0 1.5 0.8 –20 0.5 0 –0.5 –1.0 –30 0.4 AMPLITUDE (dBFS) DNL ERROR (LSB) INL ERROR (LSB) 0 –10 0.6 1.0 0.2 0 –0.2 –0.4 –0.8 0 4096 8192 12288 OUTPUT CODE –1.
PAGE 12
LTC2268-14/ LTC2267-14/LTC2266-14 Typical Performance Characteristics LTC2268-14: SFDR vs Input Frequency, –1dB, 2V Range, 125Msps 110 95 LTC2268-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps 90 80 75 70 SNR (dBc AND dBFS) 85 dBc 60 50 40 30 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 350 226814 G10 0 –60 0 30 –10 73 72 1-LANE, 3.5mA IOVDD (mA) 20 2-LANE, 1.
PAGE 13
LTC2268-14/ LTC2267-14/LTC2266-14 Typical Performance Characteristics 0 LTC2267-14: 8k Point FFT, fIN = 70MHz, –1dBFS, 105Msps 0 –10 –10 –20 –20 –20 –30 –30 –30 –40 –50 –60 –70 –80 AMPLITUDE (dBFS) –10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 LTC2267-14: 8k Point FFT, fIN = 30MHz, –1dBFS, 105Msps –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –100 –90 –100 –90 –100 –110 –120 –110 –120 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 0 10 20 30 40 FREQUENCY (MHz) 226814 G24 50 20 30 40 F
PAGE 14
LTC2268-14/ LTC2267-14/LTC2266-14 Typical Performance Characteristics LTC2267-14: SNR vs SENSE, fIN = 5MHz, –1dB LTC2266-14: Integral Nonlinearity (INL) 73 1.5 72 1.0 SNR (dBFS) 71 70 69 –0.5 67 –1.5 66 –2.0 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 0.6 0 –1.0 0.7 0.8 0.5 68 0.6 1.0 DNL ERROR (LSB) 2.0 INL ERROR (LSB) 74 0.2 0 –0.2 –0.4 –0.8 0 4096 8192 12288 OUTPUT CODE –1.
PAGE 15
LTC2268-14/ LTC2267-14/LTC2266-14 Typical Performance Characteristics LTC2266-14: SNR vs Input Frequency, –1dB, 2V Range, 80Msps LTC2266-14: SFDR vs Input Frequency, –1dB, 2V Range, 80Msps LTC2266-14: SFDR vs Input Frequency, –1dB, 2V Range, 80Msps 74 110 95 100 73 90 70 69 SFDR (dBc AND dBFS) SFDR (dBFS) SNR (dBFS) 71 85 80 75 68 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 dBc 60 50 40 30 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) DCO Cycle-Cycle Jitter vs Serial Dat
PAGE 16
LTC2268-14/ LTC2267-14/LTC2266-14 Pin Functions AIN1+ (Pin 1): Channel 1 Positive Differential Analog Input. AIN1– (Pin 2): Channel 1 Negative Differential Analog Input. VCM1 (Pin 3): Common Mode Bias Output, Nominally Equal to VDD/2. VCM should be used to bias the common mode of the analog inputs of channel 1. Bypass to ground with a 0.1µF ceramic capacitor. REFH (Pins 4,5): ADC High Reference. Bypass to pins 6, 7 with a 2.2µF ceramic capacitor and to ground with a 0.1µF ceramic capacitor.
PAGE 17
LTC2268-14/ LTC2267-14/LTC2266-14 Pin Functions become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal. VREF (Pin 36): Reference Voltage Output. Bypass to ground with a 1µF ceramic capacitor, nominally 1.25V. SENSE (Pin 38): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range.
PAGE 18
LTC2268-14/ LTC2267-14/LTC2266-14 Block Diagram 1.8V 1.8V ENC+ VDD ENC– OVDD OUT1A+ AIN1 AIN1– OUT1A– PLL + OUT1B+ OUT1B– 14-BIT ADC CORE SAMPLEAND-HOLD OUT2A+ AIN2– OUT2A– DATA SERIALIZER AIN2+ OUT2B+ 14-BIT ADC CORE SAMPLEAND-HOLD OUT2B– DCO+ VREF 1µF 1.25V REFERENCE DCO– FR+ RANGE SELECT FR– OGND REFH REF BUF SENSE REFL VDD /2 DIFF REF AMP GND MODE CONTROL REGISTERS REFH REFL VCM1 VCM2 PAR/SER CS SCK SDI SDO 226814 F01 0.1µF 0.1µF 0.1µF 2.2µF 0.1µF 0.
PAGE 19
LTC2268-14/ LTC2267-14/LTC2266-14 Applications Information CONVERTER OPERATION ANALOG INPUT The LTC2268-14/LTC2267-14/LTC2266-14 are low power, 2-channel, 14-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. To minimize the number of data lines the digital outputs are serial LVDS.
PAGE 20
LTC2268-14/ LTC2267-14/LTC2266-14 Applications Information Transformer Coupled Circuits Amplifier Circuits Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion. Figure 7 shows the analog input being driven by a high speed differential amplifier.
PAGE 21
LTC2268-14/ LTC2267-14/LTC2266-14 Applications Information Reference The LTC2268-14/LTC2267-14/LTC2266-14 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V.
PAGE 22
LTC2268-14/ LTC2267-14/LTC2266-14 Applications Information The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC– should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode.
PAGE 23
LTC2268-14/ LTC2267-14/LTC2266-14 Applications Information Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2268-14. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTC2267-14) or 80MHz (LTC2266-14). SERIALIZATION MODE MAXIMUM SAMPLING FREQUENCY, fS (MHz) DCO FREQUENCY FR FREQUENCY SERIAL DATA RATE 2-Lane 16-Bit Serialization 125 4 • fS fS 8 • fS 2-Lane 14-Bit Serialization 125 3.5 • fS 0.
PAGE 24
LTC2268-14/ LTC2267-14/LTC2266-14 Applications Information The digital output is randomized by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied—an exclusive-OR operation is applied between the LSB and all other bits. The FR and DCO outputs are not affected. The output randomizer is enabled by serially programming mode control register A1.
PAGE 25
LTC2268-14/ LTC2267-14/LTC2266-14 Applications Information Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0).
PAGE 26
LTC2268-14/ LTC2267-14/LTC2266-14 Applications Information REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 ILVDS2 D6 D5 D4 D3 D2 D1 D0 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE2 OUTMODE1 OUTMODE0 Bits 7-5 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.
PAGE 27
LTC2268-14/ LTC2267-14/LTC2266-14 Applications Information GROUNDING AND BYPASSING The LTC2268-14/LTC2267-14/LTC2266-14 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible.
PAGE 28
LTC2268-14/ LTC2267-14/LTC2266-14 TYPICAL APPLICATIONS Inner Layer 2 GND Inner Layer 3 Inner Layer 4 Inner Layer 5 Power Bottom Side Silkscreen Bottom 22687614fa 28
PAGE 29
LTC2268-14/ LTC2267-14/LTC2266-14 TYPICAL APPLICATIONS LTC2268 Schematic PAR/SER C4 1µF SDO SENSE VDD C5 1µF R92 100 10 OUT1A– OUT1A+ SDO GND PAR/SER GND VREF DCO– 27 LTC2268 REFH OVDD 26 25 REFL OGND REFL FR+ VCM2 FR– AIN2+ OUT2A+ 22 – OUT2A– 21 AIN2 AIN2 OUT2B+ 9 C59 0.1µF REFH OUT2B– 8 28 GND 7 DCO+ SDI AIN2 6 VCM1 SCK C3 0.1µF C30 0.1µF 29 AIN1 CS C2 0.1µF C1 2.
PAGE 30
LTC2268-14/ LTC2267-14/LTC2266-14 Package Description UJ Package 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 0.05 6.50 0.05 5.10 0.05 4.42 0.05 4.50 0.05 (4 SIDES) 4.42 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 0.10 (4 SIDES) 0.75 0.05 R = 0.10 TYP R = 0.115 TYP 39 40 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 4.50 REF (4-SIDES) 4.42 0.10 2 PIN 1 NOTCH R = 0.45 OR 0.
PAGE 31
LTC2268-14/ LTC2267-14/LTC2266-14 Revision History REV DATE DESCRIPTION A 6/11 Revised AIN+ and AIN– in Pin Functions section to match Pin Configuration PAGE NUMBER 16 Revised Software Reset paragraph and Table 4 in Applications Information section 25 Added VDD to LTC2268 Schematic in Typical Applications section 29 22687614fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 32
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