Datasheet

LTC2265-12/
LTC2264-12/LTC2263-12
9
22654312fb
TIMING DIAGRAMS
2-Lane Output Mode, 12-Bit Serialization
226512 TD03
t
AP
N + 1
N
ANALOG
INPUT
ENC
–
DCO
–
FR
+
ENC
+
DCO
+
FR
–
OUT#A
+
SAMPLE N-6 SAMPLE N-5
OUT#A
–
OUT#B
+
OUT#B
–
SAMPLE N-4
t
FRAME
t
DATA
t
SER
t
SER
t
PD
D7 D5 D3 D1 D11 D9 D7 D5 D3 D1 D11 D9 D7
D6 D4 D2 D0 D10 D8 D6 D4 D2 D0 D10 D8 D6
t
ENCH
t
ENCL
t
SER
226512 TD04
t
AP
N + 1
N
ANALOG
INPUT
ENC
–
DCO
–
FR
–
ENC
+
DCO
+
FR
+
OUT#A
+
OUT#B
+
, OUT#B
–
ARE DISABLED
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
OUT#A
–
t
FRAME
t
DATA
t
SER
t
SER
t
PD
D
X
* D
Y
* 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D
X
*
D
Y
* 0 0 D11 D10 D9 D8
t
ENCH
t
ENCL
t
SER
*D
X
AND D
Y
ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D
X
AND D
Y
ARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
1-Lane Output Mode, 16-Bit Serialization