Datasheet

10
22654312fb
LTC2265-12/
LTC2264-12/LTC2263-12
TIMING DIAGRAMS
1-Lane Output Mode, 14-Bit Serialization
1-Lane Output Mode, 12-Bit Serialization
226512 TD05
t
AP
N + 1
N
ANALOG
INPUT
ENC
–
DCO
–
FR
–
ENC
+
DCO
+
FR
+
OUT#A
+
OUT#B
+
, OUT#B
–
ARE DISABLED
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
OUT#A
–
t
FRAME
t
DATA
t
SER
t
SER
t
PD
D1 D0 D
X
* D
Y
* D
Y
*D
X
*D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8
t
ENCH
t
ENCL
t
SER
*D
X
AND D
Y
ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D
X
AND D
Y
ARE SET TO
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
226512 TD06
t
AP
N + 1
N
ANALOG
INPUT
ENC
–
DCO
–
FR
–
ENC
+
DCO
+
FR
+
OUTA
+
OUTB
+
, OUTB
–
ARE DISABLED
SAMPLE N-6 SAMPLE N-5 SAMPLE N-4
OUTA
–
t
FRAME
t
DATA
t
SER
t
SER
t
PD
D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9
t
ENCH
t
ENCL
t
SER