LTC2261-14 LTC2260-14/LTC2259-14 14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs Features n n n n n n n n n n n n n Description The LTC®2261-14/LTC2260-14/LTC2259-14 are sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 73.4dB SNR and 85dB spurious free dynamic range (SFDR). Ultralow jitter of 0.
LTC2261-14 LTC2260-14/LTC2259-14 Absolute Maximum Ratings (Notes 1, 2) Supply Voltages (VDD, OVDD)........................ –0.3V to 2V Analog Input Voltage (AIN+, AIN –, PAR/SER, SENSE) (Note 3)........... –0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4)..................................... –0.3V to 3.9V SDO (Note 4).............................................. –0.3V to 3.9V Digital Output Voltage................. –0.3V to (OVDD + 0.
LTC2261-14 LTC2260-14/LTC2259-14 Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2261CUJ-14#PBF LTC2261CUJ-14#TRPBF LTC2261UJ-14 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C LTC2261IUJ-14#PBF LTC2261IUJ-14#TRPBF LTC2261UJ-14 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C LTC2260CUJ-14#PBF LTC2260CUJ-14#TRPBF LTC2260UJ-14 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C LTC2260IUJ-14#PBF LTC2260IUJ-14#TRPBF LTC2260UJ-14 40-Lead (6mm × 6m
LTC2261-14 LTC2260-14/LTC2259-14 Analog Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l Differential Analog Input (Note 8) l VCM – 100mV VCM VCM + 100mV V l 0.625 1.250 1.
LTC2261-14 LTC2260-14/LTC2259-14 Digital Inputs and Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) VID Differential Input Voltage (Note 8) l 0.2 VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 l 0.2 V 1.2 1.6 V V 3.
LTC2261-14 LTC2260-14/LTC2259-14 Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN LTC2261-14 TYP MAX MIN LTC2260-14 TYP MAX LTC2259-14 MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double-Data Rate VDD Analog Supply Voltage (Note 10) l 1.7 OVDD Output Supply Voltage (Note 10) l 1.1 1.
LTC2261-14 LTC2260-14/LTC2259-14 timing characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (LVDS Mode) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 5.
LTC2261-14 LTC2260-14/LTC2259-14 timing DIAGRAMS Double-Data Rate CMOS Output Mode Timing All Outputs Are Single Ended and Have CMOS Levels tAP ANALOG INPUT N+4 N+2 N N+3 tH tL N+1 ENC– ENC+ tD D0_1 tD D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 D12N-5 D13N-5 D12N-4 D13N-4 D12N-3 D13N-3 D12N-2 D13N-2 •• • D12_13 OFN-5 OF OFN-4 OFN-2 tC tC CLKOUT+ OFN-3 CLKOUT – 226114 TD02 Double-Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels tAP A
LTC2261-14 LTC2260-14/LTC2259-14 timing DIAGRAMS SPI Port Timing (Readback Mode) tDS tS tDH tSCK tH CS SCK tDO SDI A6 R/W SDO A5 A4 A3 A2 A1 A0 XX XX D7 HIGH IMPEDANCE XX D6 D5 XX XX D4 XX D3 D2 XX XX D1 D0 SPI Port Timing (Write Mode) CS SCK SDI A6 R/W SDO A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 226114 TD04 HIGH IMPEDANCE Typical Performance Characteristics LTC2261-14: Integral Non-Linearity (INL) LTC2261-14: Differential Non-Linearity (DNL) 2.0 1.
LTC2261-14 LTC2260-14/LTC2259-14 Typical Performance Characteristics LTC2261-14: 8k Point FFT, fIN = 70MHz –1dBFS, 125Msps LTC2261-14: 8k Point FFT, fIN = 140MHz –1dBFS, 125Msps 0 0 –10 –10 –20 –20 –20 –30 –30 –30 –40 –50 –60 –70 –80 AMPLITUDE (dBFS) 0 –10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2261-14: 8k Point FFT, fIN = 30MHz –1dBFS, 125Msps –40 –50 –60 –70 –80 –60 –70 –80 –90 –100 –90 –100 –90 –100 –110 –120 –110 –120 –110 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 0 10 20 3
LTC2261-14 LTC2260-14/LTC2259-14 Typical Performance Characteristics LTC2261-14: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, 5pF on Each Data Output 45 74 3.5mA LVDS 40 73 35 71 SNR (dBFS) 1.75mA LVDS 20 70 69 15 68 10 1.8V CMOS 5 67 1.2V CMOS 0 25 50 75 100 SAMPLE RATE (Msps) 66 125 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 226114 G14 60 LTC2260-14: Integral Non-Linearity (INL) 2.0 LVDS 1.5 CMOS 1.0 72 DDR CMOS SNR (dBFS) AMPLITUDE (dBFS) 74 70 0.5 0 –0.5 –1.
LTC2261-14 LTC2260-14/LTC2259-14 Typical Performance Characteristics LTC2260-14: 8k Point 2-Tone FFT, fIN = 70MHz, 75MHz, –1dBFS, 105Msps LTC2260-14: 8k Point FFT, fIN = 140MHz –1dBFS, 105Msps 0 0 –10 –10 –20 –20 –20 –30 –30 –30 –40 –50 –60 –70 –80 AMPLITUDE (dBFS) 0 –10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2260-14: 8k Point FFT, fIN = 70MHz –1dBFS, 105Msps –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –100 –90 –100 –90 –100 –110 –120 –110 –120 –110 –120 0 10 20 30 40 FREQUENCY (MHz
LTC2261-14 LTC2260-14/LTC2259-14 Typical Performance Characteristics LTC2260-14: SNR vs SENSE, fIN = 5MHz, –1dB LTC2259-14: Integral Non-Linearity (INL) 2.0 1.0 73 1.5 0.8 72 1.0 SNR (dBFS) 70 69 0.5 0 –0.5 68 –1.0 67 –1.5 66 –2.0 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 0.6 0.4 DNL ERROR (LSB) INL ERROR (LSB) 74 71 0.2 0 –0.2 –0.4 –0.6 –0.8 0 4096 8192 12288 OUTPUT CODE 226114 G35 –1.
LTC2261-14 LTC2260-14/LTC2259-14 Typical Performance Characteristics LTC2259-14: SNR vs Input Frequency, –1dB, 2V Range, 80Msps LTC2259-14: SFDR vs Input Frequency, –1dB, 2V Range, 80Msps LTC2259-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 80Msps 95 74 73 110 100 90 70 69 SFDR (dBc AND dBFS) SFDR (dBFS) SNR (dBFS) 72 71 85 80 75 68 66 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 350 0 dBc 60 50 40 30 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 45 74 73 35 LVDS OUTPUTS 72
LTC2261-14 LTC2260-14/LTC2259-14 Pin Functions Pins That Are the Same for All Digital Output Modes AIN+ (Pin 1): Positive Differential Analog Input. AIN– (Pin 2): Negative Differential Analog Input. GND (Pin 3): ADC Power Ground. REFH (Pins 4, 5): ADC High Reference. Bypass to Pins 6, 7 with a 2.2µF ceramic capacitor and to ground with a 0.1µF ceramic capacitor. REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins 4, 5 with a 2.2µF ceramic capacitor and to ground with a 0.1µF ceramic capacitor.
LTC2261-14 LTC2260-14/LTC2259-14 Pin Functions Full-Rate CMOS Output Mode All Pins Below Have CMOS Output Levels (OGND to OVDD) D0 to D13 (Pins 17-24, 29-34): Digital Outputs. D13 is the MSB. CLKOUT– (Pin 27): Inverted Version of CLKOUT+. CLKOUT+ (Pin 28): Data Output Clock. The digital outputs normally transition at the same time as the falling edge of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers.
LTC2261-14 LTC2260-14/LTC2259-14 Functional Block Diagram AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE VDD FIFTH PIPELINED ADC STAGE GND VDD/2 0.1µF VREF 1µF 1.25V REFERENCE SHIFT REGISTER AND CORRECTION RANGE SELECT SENSE REFH REF BUF REFL INTERNAL CLOCK SIGNALS OVDD OF DIFF REF AMP MODE CONTROL REGISTERS CLOCK/DUTY CYCLE CONTROL • • • OUTPUT DRIVERS D13 D0 CLKOUT + CLKOUT – REFH 0.
LTC2261-14 LTC2260-14/LTC2259-14 Applications Information CONVERTER OPERATION The LTC2261-14/LTC2260-14/LTC2259-14 are low power 14-bit 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially, or single ended for lower power consumption.
LTC2261-14 LTC2260-14/LTC2259-14 Applications Information DC level. At higher input frequencies a transmission line balun transformer (Figures 4 to 6) has better balance, resulting in lower A/D distortion. Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC-coupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion.
LTC2261-14 LTC2260-14/LTC2259-14 Applications Information Reference The LTC2261-14/LTC2260-14/LTC2259-14 have an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9.) The VREF , REFH and REFL pins should be bypassed as shown in Figure 8. The 0.
LTC2261-14 LTC2260-14/LTC2259-14 Applications Information Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10) and the single-ended encode mode (Figure 11).
LTC2261-14 LTC2260-14/LTC2259-14 Applications Information For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50%(±5%) duty cycle. The duty cycle stabilizer should not be used below 5Msps. When using double-data rate CMOS at high sample rates the SNR will degrade slightly (see Typical Performance Characteristics section).
LTC2261-14 LTC2260-14/LTC2259-14 Applications Information Phase Shifting the Output Clock DATA FORMAT In full-rate CMOS mode the data output bits normally change at the same time as the falling edge of CLKOUT+, so the rising edge of CLKOUT+ can be used to latch the output data. In double-data rate CMOS and LVDS modes the data output bits normally change at the same time as the falling and rising edges of CLKOUT+.
LTC2261-14 LTC2260-14/LTC2259-14 Applications Information Digital Output Randomizer Alternate Bit Polarity Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude.
LTC2261-14 LTC2260-14/LTC2259-14 Applications Information The digital output is decoded at the receiver by inverting the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate bit polarity mode is independent of the digital output randomizer—either, both or neither function can be on at the same time. When alternate bit polarity mode is on, the data format is offset binary and the 2’s complement control bit has no effect.
LTC2261-14 LTC2260-14/LTC2259-14 Applications Information Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK.
LTC2261-14 LTC2260-14/LTC2259-14 Applications Information REGISTER A2: TIMING REGISTER (ADDRESS 02h) D7 X D6 D5 D4 D3 D2 D1 D0 X X X CLKINV CLKPHASE1 CLKPHASE0 DCS Bits 7-4 Unused, Don’t Care Bits.
LTC2261-14 LTC2260-14/LTC2259-14 Applications Information REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h) D7 D6 D5 D4 D3 D2 D1 D0 X X OUTTEST2 OUTTEST1 OUTTEST0 ABP RAND TWOSCOMP Bit 7-6 Unused, Don’t Care Bits. Bits 5-3 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits 000 = Digital Output Test Patterns Off 001 = All Digital Outputs = 0 011 = All Digital Outputs = 1 101 = Checkerboard Output Pattern.
LTC2261-14 LTC2260-14/LTC2259-14 Typical Applications LTC2261 Schematic T2 MABAES0060 • R9 10Ω • SENSE R39 33.2Ω 1% ANALOG INPUT R10 10Ω R40 33.2Ω 1% C12 0.1µF R14 1k C51 4.7pF C17 1µF VDD R15 100Ω C23 1µF C13 1µF R16 100Ω C19 0.1µF 40 39 38 37 VDD SENSE VREF VCM R27 10Ω 1 R28 10Ω 2 3 4 C15 0.1µF C20 2.2µF 5 6 7 C21 0.1µF VDD PAR/SER 8 9 10 C18 0.
LTC2261-14 LTC2260-14/LTC2259-14 TYPICAL APPLICATIONS Top Side Silkscreen Top 226114 TA04 226114 TA03 Inner Layer 2 GND Inner Layer 3 226114 TA04 30 226114 TA06 226114fc For more information www.linear.
LTC2261-14 LTC2260-14/LTC2259-14 TYPICAL APPLICATIONS Inner Layer 4 Inner Layer 5 Power 226114 TA08 226114 TA07 Bottom Side 226114 TA09 226114fc For more information www.linear.
LTC2261-14 LTC2260-14/LTC2259-14 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UJ Package 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 ±0.05 6.50 ±0.05 5.10 ±0.05 4.42 ±0.05 4.50 ±0.05 (4 SIDES) 4.42 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 ±0.10 (4 SIDES) 0.75 ±0.05 R = 0.10 TYP R = 0.
LTC2261-14 LTC2260-14/LTC2259-14 Revision History (Revision history begins at Rev B) REV DATE DESCRIPTION B 08/12 Corrected IOVDD to IOVDD. 14 Corrected RESET REGISTER A0, D7 description. 26 Attached VDD to pins 9,10 and 40 on schematic. 29 Corrected “external reference” to “internal reference” for 1V input range. 20 C 01/14 PAGE NUMBER 226114fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
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