Datasheet

LTC2261-12
LTC2260-12/LTC2259-12
6
226112fc
For more information www.linear.com/LTC2261-12
power requireMenTs
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS
LTC2261-12 LTC2260-12 LTC2259-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
CMOS Output Modes: Full-Data Rate and Double-Data Rate
V
DD
Analog Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OV
DD
Output Supply Voltage (Note 10)
l
1.1 1.9 1.1 1.9 1.1 1.9 V
I
VDD
Analog Supply Current DC Input
Sine Wave Input
l
68.7
70
81.1
57.1
58.3
67.4
48
49
56.6
mA
mA
I
OVDD
Digital Supply Current Sine Wave Input, OV
DD
=1.2V 3.5 2.9 2.2 mA
P
DISS
Power Dissipation DC Input
Sine Wave Input, OV
DD
=1.2V
l
124
130
146 103
108
122 87
91
102 mW
mW
LVDS Output Mode
V
DD
Analog Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OV
DD
Output Supply Voltage (Note 10)
l
1.7 1.9 1.7 1.9 1.7 1.9 V
I
VDD
Analog Supply Current Sine Wave Input
l
73.6 86.9 61.9 73.1 52.7 62.2 mA
I
OVDD
Digital Supply Current
(0V
DD
= 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
l
18.8
36.7
22.2
43.3
18.8
36.7
22.2
43.3
18.8
36.7
22.2
43.3
mA
mA
P
DISS
Power Dissipation Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
l
166
199
196
235
145
177
172
210
129
161
152
190
mW
mW
All Output Modes
P
SLEEP
Sleep Mode Power 0.5 0.5 0.5 mW
P
NAP
Nap Mode Power 9 9 9 mW
P
DIFFCLK
Power Increase with Differential Encode Mode Enabled
(No Increase for Nap or Sleep Modes)
10 10 10 mW
TiMing characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2261-12 LTC2260-12 LTC2259-12
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
f
S
Sampling Frequency (Note 10)
l
1 125 1 105 1 80 MHz
t
L
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2.0
4
4
500
500
4.52
2.00
4.76
4.76
500
500
5.93
2.00
6.25
6.25
500
500
ns
ns
t
H
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
3.8
2.0
4
4
500
500
4.52
2.00
4.76
4.76
500
500
5.93
2.00
6.25
6.25
500
500
ns
ns
t
AP
Sample-and-Hold
Acquisition Delay Time
0 0 0 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (CMOS Modes: Full-Data Rate and Double-Data Rate)
t
D
ENC to Data Delay C
L
= 5pF (Note 8)
l
1.1 1.7 3.1 ns
t
C
ENC to CLKOUT Delay C
L
= 5pF (Note 8)
l
1 1.4 2.6 ns
t
SKEW
DATA to CLKOUT Skew t
D
– t
C
(Note 8)
l
0 0.3 0.6 ns
Pipeline Latency Full-Data Rate Mode
Double-Data Rate Mode
5.0
5.5
Cycles
Cycles