Datasheet
LTC2258-14
LTC2257-14/LTC2256-14
6
225814fc
For more information www.linear.com/LTC2258-14For more information www.linear.com/LTC2258-14
power requireMenTs
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 9)
SYMBOL PARAMETER CONDITIONS
LTC2258-14 LTC2257-14 LTC2256-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
CMOS Output Modes: Full Data Rate and Double Data Rate
V
DD
Analog Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OV
DD
Output Supply Voltage (Note 10)
l
1.1 1.9 1.1 1.9 1.1 1.9 V
I
VDD
Analog Supply Current DC Input
Sine Wave Input
l
44.7
45.3
49.5 27
27.9
30 19.5
19.9
22 mA
mA
I
OVDD
Digital Supply Current Sine Wave Input, OV
DD
=1.2V 2.6 1.6 1.1 mA
P
DISS
Power Dissipation DC Input
Sine Wave Input, OV
DD
=1.2V
l
80.5
84.7
90 48.6
52.1
54 35.1
37.1
40 mW
mW
LVDS Output Mode
V
DD
Analog Supply Voltage (Note 10)
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
OV
DD
Output Supply Voltage (Note 10)
l
1.7 1.9 1.7 1.9 1.7 1.9 V
I
VDD
Analog Supply Current Sine Wave Input
l
48.9 54 31.4 35 23.5 26 mA
I
OVDD
Digital Supply Current
(0V
DD
= 1.8V)
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
l
20.7
40.5
23
44
20.7
40.5
23
44
20.7
40.5
23
44
mA
mA
P
DISS
Power Dissipation Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
l
125.3
160.9
139
177
93.8
129.4
105
143
79.6
115.2
89
126
mW
mW
All Output Modes
P
SLEEP
Sleep Mode Power 0.5 0.5 0.5 mW
P
NAP
Nap Mode Power 9 9 9 mW
P
DIFFCLK
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
10 10 10 mW
TiMing characTerisTics
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC2258-14 LTC2257-14 LTC2256-14
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
f
S
Sampling Frequency (Note 10)
l
1 65 1 40 1 25 MHz
t
L
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2.0
7.69
7.69
500
500
11.88
2.00
12.5
12.5
500
500
19
2.00
20
20
500
500
ns
ns
t
H
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
l
l
7.3
2.0
7.69
7.69
500
500
11.88
2.00
12.5
12.5
500
500
19
2.00
20
20
500
500
ns
ns
t
AP
Sample-and-Hold
Acquisition Delay Time
0 0 0 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
t
D
ENC to Data Delay C
L
= 5pF (Note 8)
l
1.1 1.7 3.1 ns
t
C
ENC to CLKOUT Delay C
L
= 5pF (Note 8)
l
1 1.4 2.6 ns
t
SKEW
DATA to CLKOUT Skew t
D
– t
C
(Note 8)
l
0 0.3 0.6 ns
Pipeline Latency Full Data Rate Mode
Double Data Rate Mode
5.0
5.5
Cycles
Cycles