Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QFN 32

LTC2251/LTC2250

22510fa

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

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Sample Rate: 125Msps/105Msps

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Single 3V Supply (2.85V to 3.4V)

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Low Power: 395mW/320mW

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61.6dB SNR

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85dB SFDR

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No Missing Codes

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Flexible Input: 1V

P-P

to 2V

P-P

Range

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640MHz Full Power Bandwidth S/H

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Clock Duty Cycle Stabilizer

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Shutdown and Nap Modes

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Pin Compatible Family:

125Msps: LTC2251 (10-Bit), LTC2253 (12-Bit)

105Msps: LTC2250 (10-Bit), LTC2252 (12-Bit)

80Msps: LTC2239 (10-Bit), LTC2229 (12-Bit)

65Msps: LTC2238 (10-Bit), LTC2228 (12-Bit)

40Msps: LTC2237 (10-Bit), LTC2227 (12-Bit)

25Msps: LTC2236 (10-Bit), LTC2226 (12-Bit)

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32-Pin (5mm × 5mm) QFN Package

10-Bit, 125/105Msps

Low Noise 3V ADCs

The LTC

2251/LTC2250 are 10-bit 125Msps/105Msps,

low noise 3V A/D converters designed for digitizing high

frequency, wide dynamic range signals. The LTC2251/

LTC2250 are perfect for demanding imaging and commu-

nications applications with AC performance that includes

61.6dB SNR and 85dB SFDR for signals at the Nyquist

frequency.

DC specs include ±0.1LSB INL (typ), ±0.05LSB DNL (typ)

and ±0.6LSB INL, ±0.6LSB DNL over temperature. The

transition noise is a low 0.08LSB

RMS

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.3V

logic.

A single-ended CLK input controls converter operation. An

optional clock duty cycle stabilizer allows high perfor-

mance at full speed for a wide range of clock duty cycles.

LTC2251: SNR vs Input Frequency,

–1dB, 2V Range, 125Msps

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Wireless and Wired Broadband Communication

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Imaging Systems

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Ultrasound

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Spectral Analysis

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Portable Instrumentation

–

INPUT

S/H

CORRECTION

LOGIC

OUTPUT

DRIVERS

10-BIT

PIPELINED

ADC CORE

CLOCK/DUTY

CYCLE

CONTROL

FLEXIBLE

REFERENCE

•

CLK

REFH

REFL

ANALOG

INPUT

22510 TA01

OGND

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

INPUT FREQUENCY (MHz)

SNR (dBFS)

100

200

250

22510 G09

150

300

350

Summary of content (24 pages)

PAGE 1
LTC2251/LTC2250 10-Bit, 125/105Msps Low Noise 3V ADCs U FEATURES DESCRIPTIO ■ The LTC®2251/LTC2250 are 10-bit 125Msps/105Msps, low noise 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2251/ LTC2250 are perfect for demanding imaging and communications applications with AC performance that includes 61.6dB SNR and 85dB SFDR for signals at the Nyquist frequency. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Sample Rate: 125Msps/105Msps Single 3V Supply (2.85V to 3.
PAGE 2
LTC2251/LTC2250 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO OVDD = VDD (Notes 1, 2) ORDER PART NUMBER D7 D8 D9 OF MODE SENSE VCM TOP VIEW VDD Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.
PAGE 3
LTC2251/LTC2250 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ –AIN–) 2.85V < VDD < 3.4V (Note 7) ● VIN,CM Analog Input Common Mode Differential Input (Note 7) ● 1 1.
PAGE 4
LTC2251/LTC2250 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V ±25 VCM Output Tempco ppm/°C VCM Line Regulation 2.85V < VDD < 3.4V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 5
LTC2251/LTC2250 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) MIN LTC2251 TYP MAX MIN LTC2250 TYP MAX SYMBOL PARAMETER CONDITIONS UNITS VDD Analog Supply Voltage (Note 9) ● 2.85 3 3.4 2.85 3 3.4 V OVDD Output Supply Voltage (Note 9) ● 0.5 3 3.6 0.5 3 3.
PAGE 6
LTC2251/LTC2250 U W TYPICAL PERFOR A CE CHARACTERISTICS 1.0 1.0 0 0.8 0.8 –10 0.6 0.6 –20 0.4 0.4 0 –0.2 –0.4 0.2 0 –0.2 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.
PAGE 7
LTC2251/LTC2250 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2251: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2251: SFDR vs Input Frequency, –1dB, 2V Range, 125Msps 90 95 80 70 SFDR 85 80 75 dBFS 80 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) 90 70 SNR 60 60 50 40 dBc 30 20 70 10 50 65 0 100 150 200 250 300 350 INPUT FREQUENCY (MHz) 55210 G10 50 20 0 –50 40 60 80 100 120 140 160 SAMPLE RATE (Msps) 22510 G11 –40 –30 –10 –20 INPUT LEVEL (dBFS) 0 22510 G12 LTC2251: IVDD vs S
PAGE 8
LTC2251/LTC2250 U W TYPICAL PERFOR A CE CHARACTERISTICS 1.0 1.0 0 0.8 0.8 –10 0.6 0.6 –20 0.4 0.4 0 –0.2 –0.4 0.2 0 –0.2 –0.4 –40 –50 –60 –70 –80 –90 –0.6 –0.8 –0.8 –1.0 –1.
PAGE 9
LTC2251/LTC2250 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2250: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2250: SFDR vs Input Frequency, –1dB, 2V Range, 105Msps 95 90 80 70 SFDR 85 80 75 dBFS 80 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) 90 70 SNR 60 60 50 40 dBc 30 20 70 10 65 50 100 150 200 250 300 350 INPUT FREQUENCY (MHz) 55210 G25 0 20 40 60 80 100 SAMPLE RATE (Msps) 100 0 –50 140 –40 –30 –10 –20 INPUT LEVEL (dBFS) 22510 G26 0 22510 G27 120 dBFS 90 115 80
PAGE 10
LTC2251/LTC2250 U U U PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. NC (Pins 12, 13, 14, 15): Do Not Connect These Pins. AIN- (Pin 2): Negative Differential Analog Input. D0-D9 (Pins 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D9 is the MSB. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.
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LTC2251/LTC2250 W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE SIXTH PIPELINED ADC STAGE 1.5V REFERENCE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D9 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 0.1µF 22510 F01 REFL OGND CLK MODE SHDN OE 2.
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LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output.
PAGE 13
LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa.
PAGE 14
LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2251/LTC2250 can be influenced by the input drive circuitry, particularly the second and third harmonics.
PAGE 15
LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth.
PAGE 16
LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10.
PAGE 17
LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced.
PAGE 18
LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO LTC2251/LTC2250 0.1µF to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. TYPICAL DATA OUTPUT OVDD can be powered with any voltage from 500mV up to 3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. OVDD VDD 0.
PAGE 19
LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO particular importance is the 0.1µF capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402 ceramic capacitor is recommended. The large 2.2µF capacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.
PAGE 20
J3 CLOCK INPUT R8 49.9Ω C12 0.1µF VDD E1 EXT REF VCM VDD R9 1k NC7SVU04 VCM VDD 4 2 EXT REF 5 6 3 1 JP3 SENSE 4 • C19 0.1µF R10 33Ω VDD GND VDD R16 1k R15 1k 1/3VDD 2/3VDD VDD 6 4 2 GND C15 2.2µF VDD 7 GND 8 5 3 1 C8 0.1µF 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 C20 0.1µF C2 12pF C11 0.1µF VDD JP4 MODE JP2 OE C7 2.2µF R6 24.9Ω R4 24.9Ω C4 0.1µF R14 1k VDD R2 24.9Ω R3 24.9Ω C14 0.
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LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO Topside Silkscreen Top Inner Layer 2 GND 22510fa 21
PAGE 22
LTC2251/LTC2250 U W U U APPLICATIO S I FOR ATIO Bottomside Inner Layer 3 Power Silkscreen Bottom 22510fa 22
PAGE 23
LTC2251/LTC2250 U PACKAGE DESCRIPTIO UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.45 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER R = 0.115 TYP 0.75 ± 0.05 0.00 – 0.05 31 32 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.45 ± 0.10 (4-SIDES) (UH32) QFN 1004 0.200 REF NOTE: 1.
PAGE 24
LTC2251/LTC2250 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1747 12-Bit, 80Msps ADC 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package LTC1748 14-Bit, 80Msps ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package LTC1749 12-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 87dB SFDR LTC1750 14-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT1993 High Speed Differential Op Amp 600MHz BW, 75dBc Distortion at 70MHz LTC2220 12-Bit, 170Msps ADC 890mW, 67.