LTC2248/LTC2247/LTC2246 14-Bit, 65/40/25Msps Low Power 3V ADCs U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®2248/LTC2247/LTC2246 are 14-bit 65Msps/ 40Msps/25Msps, low power 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2248/LTC2247/LTC2246 are perfect for demanding imaging and communications applications with AC performance that includes 74.3dB SNR and 90dB SFDR for signals at the Nyquist frequency.
LTC2248/LTC2247/LTC2246 U W U PACKAGE/ORDER I FOR ATIO U OVDD = VDD (Notes 1, 2) D11 D12 D13 OF MODE SENSE VDD VCM TOP VIEW Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ........................................
LTC2248/LTC2247/LTC2246 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS +– –) MIN TYP MAX UNITS ±0.5V to ±1V VIN Analog Input Range (AIN 2.7V < VDD < 3.4V (Note 7) ● VIN,CM Analog Input Common Mode (AIN+ + AIN–)/2 Differential Input (Note 7) Single Ended Input (Note 7) ● ● 1 0.
LTC2248/LTC2247/LTC2246 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX VCM Output Voltage IOUT = 0 1.475 1.500 1.525 ±25 VCM Output Tempco UNITS V ppm/°C VCM Line Regulation 2.7V < VDD < 3.4V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC2248/LTC2247/LTC2246 WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN fs Sampling Frequency (Note 9) ● 1 tL CLK Low Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 7.3 5 tH CLK High Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 7.
LTC2248/LTC2247/LTC2246 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2248: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 65Msps 0 0 –10 –10 –20 –20 –30 –30 AMPLITUDE (dB) AMPLITUDE (dB) LTC2248: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 65Msps –40 –50 –60 –70 –80 –50 –60 –70 –80 –90 –90 –100 –100 –110 –110 –120 –120 0 5 30 10 15 20 25 FREQUENCY (MHz) LTC2248: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 65Msps 0 5 2248 G03 10 15 20 25 FREQUENCY (MHz) 0 0 –10 –10 –20 –20 –
LTC2248/LTC2247/LTC2246 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2248: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2248: SNR and SFDR vs Clock Duty Cycle, 65Msps 110 100 80 SFDR: DCS ON 90 80 SNR 70 60 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) SFDR dBFS 70 95 100 SNR AND SFDR (dBFS) LTC2248: SNR vs Input Level, fIN = 30MHz, 2V Range, 65Msps 90 SFDR: DCS OFF 85 80 50 dBc 40 30 20 75 SNR: DCS ON 10 SNR: DCS OFF 60 70 0 10 20 30 40 50 60 70 80 90 100 110 SAMPLE RATE (Msps)
LTC2248/LTC2247/LTC2246 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2247: 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 40Msps LTC2247: 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 40Msps 0 0 –10 –10 –20 –20 –20 –30 –30 –30 –40 –50 –60 –70 –80 AMPLITUDE (dB) 0 –10 AMPLITUDE (dB) AMPLITUDE (dB) LTC2247: 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 40Msps –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 0 5 10 15 FREQUENCY (MHz) –120
LTC2248/LTC2247/LTC2246 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2247: SFDR vs Input Level, fIN = 5MHz, 2V Range, 40Msps LTC2247: IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.
LTC2248/LTC2247/LTC2246 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2246: 8192 Point 2-Tone FFT, fIN = 10.9MHz and 13.
LTC2248/LTC2247/LTC2246 U U U PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. AIN- (Pin 2): Negative Differential Analog Input. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.
LTC2248/LTC2247/LTC2246 W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE 1.5V REFERENCE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D13 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 224876 F01 REFL 0.
LTC2248/LTC2247/LTC2246 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE input tone to the RMS value of the largest 3rd order intermodulation product. Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.
LTC2248/LTC2247/LTC2246 U W U U APPLICATIO S I FOR ATIO DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram.
LTC2248/LTC2247/LTC2246 U W U U APPLICATIO S I FOR ATIO Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2248/LTC2247/LTC2246 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sample-and-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period.
LTC2248/LTC2247/LTC2246 U W U U APPLICATIO S I FOR ATIO For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth. VCM 2.2µF 0.1µF 12Ω ANALOG INPUT AIN+ LTC2248/47/46 25Ω 0.1µF T1 0.
LTC2248/LTC2247/LTC2246 U W U U APPLICATIO S I FOR ATIO pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. a low-jitter squaring circuit before the CLK pin (see Figure 11). Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE.
LTC2248/LTC2247/LTC2246 U W U U APPLICATIO S I FOR ATIO bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact. storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2248/LTC2247/ LTC2246 is 1Msps.
LTC2248/LTC2247/LTC2246 U W U U APPLICATIO S I FOR ATIO As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2248/LTC2247/LTC2246 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF.
LTC2248/LTC2247/LTC2246 U W U U APPLICATIO S I FOR ATIO Grounding and Bypassing The LTC2248/LTC2247/LTC2246 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.
J3 CLOCK INPUT R8 49.9Ω C12 0.1µF VDD E1 EXT REF VCM VDD R9 1k R7 1k L1 BEAD NC7SVU04 VCM VDD 4 2 EXT 5 REF 6 3 1 JP3 SENSE 4 • C19 0.1µF R10 33Ω VDD GND R16 1k R15 1k R14 1k VDD 1/3VDD 2/3VDD VDD 6 4 2 GND C15 2.2µF VDD 7 GND 8 5 3 1 C8 0.1µF C2 8.2pF C11 0.1µF VDD JP4 MODE JP2 OE C7 2.2µF R6 12.4Ω VDD C4 0.1µF R4 24.9Ω R3 24.9Ω R2 12.4Ω C14 0.1µF VCM VDD VDD C9 1µF C6 1µF JP1 SHDN R5 50Ω •3 2 T1 ETC1-1T 5 1 C13 0.1µF C3 0.1µF VCM C1 0.
LTC2248/LTC2247/LTC2246 U W U U APPLICATIO S I FOR ATIO Silkscreen Top Topside Inner Layer 2 GND Inner Layer 3 Power 224876fa 22
LTC2248/LTC2247/LTC2246 U U W U APPLICATIO S I FOR ATIO Bottomside Silkscreen Bottom U PACKAGE DESCRIPTIO UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) BOTTOM VIEW—EXPOSED PAD 5.00 ± 0.10 (4 SIDES) 0.70 ±0.05 0.23 TYP (4 SIDES) R = 0.115 TYP 0.75 ± 0.05 0.00 – 0.05 31 32 PIN 1 TOP MARK (NOTE 6) 1 2 5.50 ±0.05 4.10 ±0.05 3.45 ±0.05 (4 SIDES) 3.45 ± 0.10 (4-SIDES) PACKAGE OUTLINE 0.40 ± 0.10 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 0.200 REF NOTE: 1.
LTC2248/LTC2247/LTC2246 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1748 14-Bit, 80Msps, 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain LT1994 Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver Low Distortion: –94dBc at 1MHz LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 150mW, 81.
