Datasheet

LTC2240-12
12
224012fd
TIMING DIAGRAMS
LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
t
H
t
D
t
C
t
L
N – 5 N – 4 N – 3 N – 2 N – 1
t
AP
N + 1
N + 2
N + 4
N + 3
N
ANALOG
INPUT
ENC
–
ENC
+
CLKOUT
–
CLKOUT
+
D0-D11, OF
224012 TD01
t
AP
N + 1
N + 2
N + 4
N + 3
N
ANALOG
INPUT
t
H
t
D
t
C
t
L
N – 5 N – 4 N – 3 N – 2 N – 1
ENC
–
ENC
+
CLKOUTB
CLKOUTA
DA0-DA11, OFA
DB0-DB11, OFB
224012 TD02
HIGH IMPEDANCE