Datasheet

LTC2238/LTC2237/LTC2236
20
223876fa
APPLICATIO S I FOR ATIO
WUUU
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2238/LTC2237/
LTC2236 is 65Msps (LTC2238), 40Msps (LTC2237), and
25Msps (LTC2236). For the ADC to operate properly, the
CLK signal should have a 50% (±5%) duty cycle. Each half
cycle must have at least 7.3ns (LTC2238), 11.8ns
(LTC2237), and 18.9ns (LTC2236) for the ADC internal
circuitry to have enough settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To use
the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3V
DD
or 2/3V
DD
using external resistors.
The lower limit of the LTC2238/LTC2237/LTC2236 sample
rate is determined by droop of the sample-and-hold cir-
cuits. The pipelined architecture of this ADC relies on
storing analog signals on small valued capacitors. Junc-
tion leakage will discharge the capacitors. The specified
minimum operating frequency for the LTC2238/LTC2237/
LTC2236 is 1Msps.
Figure 14. Digital Output Buffer
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
LTC2228/27/26
222876 F14
OV
DD
V
DD
V
DD
0.1µF
43Ω
TYPICAL
DATA
OUTPUT
OGND
OV
DD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Table 1. Output Codes vs Input Voltage
A
IN
+
– A
IN
–
D9 – D0 D9 – D0
(2V Range) OF (Offset Binary) (2’s Complement)
>+1.000000V 1 11 1111 1111 01 1111 1111
+0.998047V 0 11 1111 1111 01 1111 1111
+0.996094V 0 11 1111 1110 01 1111 1110
+0.001953V 0 10 0000 0001 00 0000 0001
0.000000V 0 10 0000 0000 00 0000 0000
–0.001953V 0 01 1111 1111 11 1111 1111
–0.003906V 0 01 1111 1110 11 1111 1110
–0.998047V 0 00 0000 0001 10 0000 0001
–1.000000V 0 00 0000 0000 10 0000 0000
<–1.000000V 1 00 0000 0000 10 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
DD
and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2238/LTC2237/LTC2236 should
drive a minimal capacitive load to avoid possible interac-
tion between the digital outputs and sensitive input cir-
cuitry. The output should be buffered with a device such as
an ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.