LTC2229 12-Bit, 80Msps Low Power 3V ADC U FEATURES DESCRIPTIO ■ The LTC®2229 is a 12-bit 80Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2229 is perfect for demanding imaging and communications applications with AC performance that includes 70.6dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Sample Rate: 80Msps Single 3V Supply (2.7V to 3.4V) Low Power: 211mW 70.
LTC2229 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................
LTC2229 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ – AIN–) MIN TYP MAX UNITS 2.7V < VDD < 3.4V (Note 7) ● VIN,CM Analog Input Common Mode (AIN+ + AIN–)/2 Differential Input (Note 7) Single Ended Input (Note 7) ● ● 1 0.
LTC2229 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS (CLK, OE, SHDN) VIH High Level Input Voltage VDD = 3V ● VIL Low Level Input Voltage VDD = 3V ● IIN Input Current VIN = 0V to VDD ● CIN Input Capacitance (Note 7) 2 V –10 0.
LTC2229 WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN fs Sampling Frequency (Note 9) ● 1 tL CLK Low Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 5.
LTC2229 U W TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point FFT, fIN = 30MHz, –1dB, 2V Range 8192 Point FFT, fIN = 70MHz, –1dB, 2V Range 0 0 0 –10 –10 –10 –20 –20 –20 –30 –30 –30 –50 –60 –70 –80 –90 –40 –40 AMPLITUDE (dB) AMPLITUDE (dB) –40 AMPLITUDE (dB) 8192 Point FFT, fIN = 140MHz, –1dB, 2V Range –50 –60 –70 –80 –50 –60 –70 –80 –90 –90 –100 –100 –100 –110 –110 –110 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 –120 40 0 5 10 15 20 25 30 FREQUENCY (MHz) 2229 G04 0
LTC2229 U W TYPICAL PERFOR A CE CHARACTERISTICS SFDR vs Input Level, fIN = 70MHz, 2V Range SNR vs Input Level, fIN = 70MHz, 2V Range 120 80 dBFS 110 100 60 SFDR (dBc AND dBFS) SNR (dBc AND dBFS) 70 50 dBc 40 30 20 90 80 dBc 70 100dBc SFDR REFERENCE LINE 60 50 40 30 20 10 10 0 –70 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 –70 0 2249 G13 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 2229 G14 IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.
LTC2229 U U U PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. NC (Pins 12, 13): Do Not Connect These Pins. AIN- (Pin 2): Negative Differential Analog Input. D0–D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D11 is the MSB. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.
LTC2229 W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE 1.5V REFERENCE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D11 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 0.1µF 2229 F01 REFL OGND CLK MODE SHDN OE 2.
LTC2229 WU W TI I G DIAGRA tAP ANALOG INPUT N+4 N+2 N N+3 tH N+5 N+1 tL CLK tD D0-D11, OF N–5 N–4 N–3 N–2 N–1 N 2229 TD01 2229fa 10
LTC2229 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.
LTC2229 U W U U APPLICATIO S I FOR ATIO CONVERTER OPERATION As shown in Figure 1, the LTC2229 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion.
LTC2229 U W U U APPLICATIO S I FOR ATIO Single-Ended Input Input Drive Circuits For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to 1.5V or VCM. Figure 3 shows the LTC2229 being driven by an RF transformer with a center tapped secondary.
LTC2229 U W U U APPLICATIO S I FOR ATIO Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended.
LTC2229 U W U U APPLICATIO S I FOR ATIO The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM.
LTC2229 U W U U APPLICATIO S I FOR ATIO Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced.
LTC2229 U W U U APPLICATIO S I FOR ATIO DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits and the overflow bit. Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) OF D11 – D0 (Offset Binary) D11 – D0 (2’s Complement) >+1.000000V +0.999512V +0.999024V 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 0111 1111 1111 0111 1111 1110 +0.000488V 0.000000V –0.000488V –0.
LTC2229 U W U U APPLICATIO S I FOR ATIO Output Driver Power Grounding and Bypassing Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply.
LTC2229 U W U U APPLICATIO S I FOR ATIO Clock Sources for Undersampling Undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
J3 CLOCK INPUT R8 49.9Ω C12 0.1µF VDD E1 EXT REF VCM VDD R9 1k R7 1k VCM VDD 4 2 EXT REF 5 6 3 1 JP3 SENSE NC7SVU04 NC7SVU04 C10 0.1µF C5 4.7µF 6.3V 4 • C19 0.1µF R10 33Ω VDD GND VDD R16 1k R15 1k 7 5 3 1 GND 1/3VDD 2/3VDD VDD 8 6 4 GND C15 2.2µF VDD 2 C8 0.1µF 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 C20 0.1µF C2 12pF C11 0.1µF VDD JP4 MODE JP2 OE C7 2.2µF R6 24.9Ω R4 24.9Ω C4 0.1µF R14 1k VDD R2 24.9Ω R3 24.9Ω C14 0.
LTC2229 U W U U APPLICATIO S I FOR ATIO Silkscreen Top Topside Inner Layer 2 GND 2229fa 21
LTC2229 U W U U APPLICATIO S I FOR ATIO Inner Layer 3 Power Bottomside Silkscreen Bottom 2229fa 22
LTC2229 U PACKAGE DESCRIPTIO UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.45 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.23 TYP (4 SIDES) R = 0.115 TYP 0.75 ± 0.05 0.00 – 0.05 31 32 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.45 ± 0.10 (4-SIDES) (UH) QFN 0603 0.200 REF NOTE: 1.
LTC2229 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1748 14-Bit, 80Msps, 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain LT1994 Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver Low Distortion: –94dBc at 1MHz LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 150mW, 81.
