LTC2228/LTC2227/LTC2226 12-Bit, 65/40/25Msps Low Power 3V ADCs FEATURES DESCRIPTION n The LTC®2228/LTC2227/LTC2226 are 12-bit 65Msps/ 40Msps/25Msps, low power 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2228/LTC2227/LTC2226 are perfect for demanding imaging and communications applications with AC performance that includes 71.3dB SNR and 90dB SFDR for signals at the Nyquist frequency.
LTC2228/LTC2227/LTC2226 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION OVDD = VDD (Notes 1, 2) D9 D10 D11 OF MODE SENSE VCM TOP VIEW VDD Supply Voltage (VDD) ..................................................4V Digital Output Ground Voltage (OGND) ........ –0.3V to 1V Analog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V) Digital Input Voltage......................–0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ................................
LTC2228/LTC2227/LTC2226 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN Resolution (No Missing Codes) l 12 LTC2228 TYP MAX MIN LTC2227 TYP MAX 12 MIN LTC2226 TYP MAX UNITS 12 Bits Integral Linearity Error Differential Analog Input (Note 5) l –1.1 ±0.3 1.1 –1 ±0.3 1 –1 ±0.
LTC2228/LTC2227/LTC2226 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS SFDR 5MHz Input 12.5MHz Input 20MHz Input 30MHz Input 70MHz Input 140MHz Input 5MHz Input 12.5MHz Input 20MHz Input 30MHz Input 70MHz Input 140MHz Input fIN1 = 28.2MHz, fIN2 = 26.
LTC2228/LTC2227/LTC2226 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) SYMBOL PARAMETER CONDITIONS MIN LTC2228 TYP MAX LTC2227 TYP MAX MIN MIN LTC2226 TYP MAX UNITS VDD Analog Supply Voltage (Note 9) l 2.7 3 3.4 2.7 3 3.4 2.7 3 3.4 V OVDD Output Supply Voltage (Note 9) l 0.5 3 3.6 0.5 3 3.6 0.5 3 3.6 V IVDD Supply Current l 68.
LTC2228/LTC2227/LTC2226 TYPICAL PERFORMANCE CHARACTERISTICS LTC2228: Typical INL, 2V Range, 65Msps 0 1.00 0.75 0.50 0.50 0.25 0 –0.25 –0.50 –10 –20 –30 AMPLITUDE (dB) 0.75 DNL ERROR (LSB) INL ERROR (LSB) 1.00 0.25 0 –0.25 –0.75 –1.00 –1.
LTC2228/LTC2227/LTC2226 TYPICAL PERFORMANCE CHARACTERISTICS LTC2228: SNR and SFDR vs Sample Rate, 2V Range,fIN = 5MHz, –1dB LTC2228: SFDR vs Input Frequency, –1dB, 2V Range, 65Msps 100 LTC2228: SNR and SFDR vs Clock Duty Cycle, 65Msps 110 100 95 95 85 80 75 SFDR 90 80 SNR SFDR: DCS ON SFDR: DCS OFF 90 85 80 75 SNR: DCS ON 70 70 70 65 50 100 150 INPUT FREQUENCY (MHz) 200 60 20 0 60 80 40 SAMPLE RATE (Msps) 65 100 2228 G10 SNR: DCS OFF 30 35 45 50 55 60 CLOCK DUTY CYCLE (%) 40 222
LTC2228/LTC2227/LTC2226 TYPICAL PERFORMANCE CHARACTERISTICS LTC2227: Typical INL, 2V Range, 40Msps 0 1.00 0.75 0.50 0.50 0.25 0 –0.25 –0.50 –10 –20 –30 AMPLITUDE (dB) 0.75 DNL ERROR (LSB) INL ERROR (LSB) 1.00 0.25 0 –0.25 –0.50 –0.75 –0.75 –1.00 –1.
LTC2228/LTC2227/LTC2226 TYPICAL PERFORMANCE CHARACTERISTICS LTC2227: SFDR vs Input Frequency, –1dB, 2V Range, 40Msps LTC2227: SNR and SFDR vs Sample Rate, 2V Range,fIN = 5MHz, –1dB 110 100 80 dBFS 95 85 80 75 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) 90 70 SFDR 100 SFDR (dBFS) LTC2227: SNR vs Input Level, fIN = 5MHz, 2V Range, 40Msps 90 80 SNR 60 50 dBc 40 30 20 70 70 10 65 0 –60 60 0 50 100 0 200 150 INPUT FREQUENCY (MHz) 20 40 60 SAMPLE RATE (Msps) 80 –50 –40 –30 –20 INPUT LEVE
LTC2228/LTC2227/LTC2226 TYPICAL PERFORMANCE CHARACTERISTICS LTC2226: Typical INL, 2V Range, 25Msps 0 1.00 0.75 0.50 0.50 0.25 0 –0.25 –0.50 –10 –20 –30 AMPLITUDE (dB) 0.75 DNL ERROR (LSB) INL ERROR (LSB) 1.00 0.25 0 –0.25 –0.75 –1.00 –1.
LTC2228/LTC2227/LTC2226 TYPICAL PERFORMANCE CHARACTERISTICS LTC2226: SFDR vs Input Frequency, –1dB, 2V Range, 25Msps LTC2226: SNR and SFDR vs Sample Rate, 2V Range,fIN = 5MHz, –1dB 100 LTC2226: SNR vs Input Level, fIN = 5MHz, 2V Range, 25Msps 110 80 dBFS 95 SFDR (dBFS) 85 80 75 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) 100 90 70 SFDR 90 80 SNR 50 dBc 40 30 20 70 70 10 65 50 100 60 200 150 INPUT FREQUENCY (MHz) 0 10 0 30 40 20 SAMPLE RATE (Msps) 2226 G10 0 –60 50 –50 –40 –30 –2
LTC2228/LTC2227/LTC2226 PIN FUNCTIONS AIN+ (Pin 1): Positive Differential Analog Input. NC (Pins 12, 13): Do Not Connect These Pins. AIN– (Pin 2): Negative Differential Analog Input. D0-D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D11 is the MSB. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to Pins 5, 6 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.
LTC2228/LTC2227/LTC2226 FUNCTIONAL BLOCK DIAGRAM AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE 1.5V REFERENCE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION 2.2μF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D11 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 0.1μF 222876 F01 REFL OGND CLK M0DE SHDN OE 2.
LTC2228/LTC2227/LTC2226 TIMING DIAGRAM Timing Diagram tAP ANALOG INPUT N+4 N+2 N N+3 tH N+5 N+1 tL CLK tD D0-D11, OF N–5 N–4 N–3 N–2 N–1 N 222876 TD01 222876fb 14
LTC2228/LTC2227/LTC2226 APPLICATIONS INFORMATION DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.
LTC2228/LTC2227/LTC2226 APPLICATIONS INFORMATION CONVERTER OPERATION SAMPLE/HOLD OPERATION AND INPUT DRIVE As shown in Figure 1, the LTC2228/LTC2227/LTC2226 is a CMOS pipelined multi-step converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially.
LTC2228/LTC2227/LTC2226 APPLICATIONS INFORMATION however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. Single-Ended Input For cost-sensitive applications, the analog inputs can be driven single ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged.
LTC2228/LTC2227/LTC2226 APPLICATIONS INFORMATION VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER ANALOG INPUT + 2.2μF AIN+ 2.2μF 0.1μF LTC2228/27/26 LTC2228/27/26 25Ω 25Ω 0.1μF T1 12pF – 0.1μF AIN– AIN+ 12Ω ANALOG INPUT + CM – VCM 8pF 25Ω AIN– 12Ω T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 222876 F04 222876 F06 Figure 4. Differential Drive with an Amplifier Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched.
LTC2228/LTC2227/LTC2226 TYPICAL APPLICATIONS Reference Operation Figure 9 shows the LTC2228/LTC2227/LTC2226 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.
LTC2228/LTC2227/LTC2226 APPLICATIONS INFORMATION Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 3.8dB. See the Typical Performance Characteristics section. Driving the Clock Input The CLK input can be driven directly with a CMOS or TTL level signal.
LTC2228/LTC2227/LTC2226 APPLICATIONS INFORMATION Maximum and Minimum Conversion Rates DIGITAL OUTPUTS The maximum conversion rate for the LTC2228/LTC2227/ LTC2226 is 65Msps (LTC2228), 40Msps (LTC2227), and 25Msps (LTC2226). For the ADC to operate properly, the CLK signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 7.3ns (LTC2228), 11.8ns (LTC2227), and 18.9ns (LTC2226) for the ADC internal circuitry to have enough settling time for proper operation.
LTC2228/LTC2227/LTC2226 APPLICATIONS INFORMATION digital outputs of the LTC2228/LTC2227/LTC2226 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. Lower OVDD voltages will also help reduce interference from the digital outputs.
LTC2228/LTC2227/LTC2226 TYPICAL APPLICATIONS The LTC2228/LTC2227/LTC2226 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2228/LTC2227/ LTC2226 is transferred from the die through the bottomside Exposed Pad and package leads onto the printed circuit board.
J3 CLOCK INPUT VCM VDD R9 1k R7 1k NC7SVU04 VCM VDD 4 2 EXT REF 5 6 3 1 JP3 SENSE 4 • C19 0.1μF R10 33Ω VDD GND VDD R16 1k R15 1k 1/3VDD 2/3VDD VDD 6 4 2 GND C15 2.2μF VDD 7 GND 8 5 3 1 C8 0.1μF 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 C20 0.1μF C2 12pF C11 0.1μF VDD JP4 MODE JP2 OE C7 2.2μF R6 24.9Ω R4 24.9Ω C4 0.1μF R14 1k VDD R2 24.9Ω R3 24.9Ω C14 0.1μF VCM VDD VDD C9 1μF C6 1μF JP1 SHDN R5 50Ω •3 2 T1 ETC1-1T 5 1 C13 0.1μF C3 0.
LTC2228/LTC2227/LTC2226 APPLICATIONS INFORMATION Silkscreen Top Topside Inner Layer 2 GND 222876fb 25
LTC2228/LTC2227/LTC2226 APPLICATIONS INFORMATION Inner Layer 3 Power Bottomside Silkscreen Bottom 222876fb 26
LTC2228/LTC2227/LTC2226 PACKAGE DESCRIPTION UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70 p0.05 5.50 p0.05 4.10 p0.05 3.45 p 0.05 3.50 REF (4 SIDES) 3.45 p 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 p 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.75 p 0.05 R = 0.05 TYP 0.00 – 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 s 45o CHAMFER R = 0.115 TYP 31 32 0.40 p 0.
LTC2228/LTC2227/LTC2226 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1748 14-Bit, 80Msps, 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain LT1994 Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver Low Distortion: –94dBc at 1MHz LTC2202 16-Bit, 10Msps, 3V ADC, Lowest Power 150mW, 81.
