Datasheet
LTC2203/LTC2202
23
22032fd
Data Format
The LTC2203/LTC2202 parallel digital output can be
selected for offset binary or 2’s complement format. The
format is selected with the MODE pin. This pin has a four
level logic input, centered at 0, 1/3V
DD
, 2/3V
DD
and V
DD
.
An external resistor divider can be user to set the 1/3V
DD
and 2/3V
DD
logic levels. Table 1 shows the logic states
for the MODE pin.
Table 1. MODE Pin Function
MODE OUTPUT FORMAT
CLOCK DUTY
CYCLE STABILIZER
0(GND) Offset Binary Off
1/3V
DD
Offset Binary On
2/3V
DD
2’s Complement On
V
DD
2’s Complement Off
Overfl ow Bit
An overfl ow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overfl ow or underfl ow.
Output Clock
The ADC has a delayed version of the CLK input available
as a digital output. Both a noninverted version, CLKOUT
+
and an inverted version CLKOUT
–
are provided. The
CLKOUT
+
/CLKOUT
–
can be used to synchronize the
converter data to the digital system. This is necesary
when using a sinusoidal clock. Data can be latched on the
rising edge of CLKOUT
+
or the falling edge of CLKOUT
–
.
CLKOUT
+
falls and CLKOUT
–
rises as the data outputs
are updated.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer in CMOS Mode. Each buffer is powered by OV
DD
and OGND, isolated from the ADC power and ground. The
additional N-channel transistor in the output driver allows
operation down to low voltages. The internal resistor in
series with the output makes the output appear as 50Ω
to external circuitry and eliminates the need for external
damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2203/LTC2202 should drive a
minimum capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as a
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF. A resistor in
series with the output may be used but is not required
since the ADC has a series resistor of 43Ω on chip.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
22032 F10
OV
DD
V
DD
V
DD
0.1μF
TYPICAL
DATA
OUTPUT
OGND
43Ω
OV
DD
0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
LTC2203/LTC2202
Figure 9. Equivalent Circuit for a Digital Output Buffer
APPLICATIONS INFORMATION