Datasheet

LTC2203/LTC2202
17
22032fd
Figure 1. Functional Block Diagram
ADC CLOCKS
LOW JITTER
CLOCK
DRIVER
DITHER
SIGNAL
GENERATOR
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
CLK
CORRECTION LOGIC
AND
SHIFT REGISTER
DITHM0DE
OGND
CLKOUT
+
CLKOUT
OF
D15
D14
OV
DD
D1
D0
22032 F01
INPUT
S/H
A
IN
A
IN
+
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
PGA RAND
SHDN
V
DD
GND
PGA
SENSE
V
CM
BUFFER
ADC
REFERENCE
VOLTAGE
REFERENCE
RANGE
SELECT
OE
BLOCK DIAGRAM