Datasheet

LTC2175-12/
LTC2174-12/LTC2173-12
22
21754312fa
applicaTions inForMaTion
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12 and 13).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
above V
DD
(up to 3.6V), and the common mode range is
from 1.1V to 1.6V. In the differential encode mode, ENC
–
should stay at least 200mV above ground to avoid falsely
triggering the single-ended encode mode. For good jitter
performance ENC
+
should have fast rise and fall times.
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC
–
is connected
to ground and ENC
+
is driven with a square wave encode
input. ENC
+
can be taken above V
DD
(up to 3.6V) so 1.8V
to 3.3V CMOS logic levels can be used. The ENC
+
threshold
is 0.9V. For good jitter performance ENC
+
should have fast
rise and fall times.
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25µs to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
Figure 13. PECL or LVDS Encode Drive
Figure 12. Sinusoidal Encode Drive
50Ω
100Ω
0.1µF
0.1µF
0.1µF
T1
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50Ω
LTC2175-12
217512 F12
ENC
–
ENC
+
ENC
+
ENC
–
PECL OR
LVDS
CLOCK
0.1µF
0.1µF
217512 F13
LTC2175-12