Datasheet

LTC2158-14
20
215814f
applicaTions inForMaTion
Table 3. Serial Programming Mode Register Map (PAR/SER = GND). X indicates an unused bit that is read back as 0
REGISTER A0: RESET REGISTER (ADDRESS 00h) Write Only
D7 D6 D5 D4 D3 D2 D1 D0
RESET X X X X X X X
Bit 7 RESET Software Reset Bit
0 = Reset Disabled
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Bits 6-0 Unused Bits
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X SLEEP NAP PDB 0
Bits 7-4 Unused Bit
Bit 3 SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2 NAP
0 = Normal Mode
1 = Low Power Mode for Both Channels
Bit 1 PDB
0 = Normal Operation
1 = Power Down Channel B. Channel A operates normally.
Bit 0 Must be set to 0
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7 D6 D5 D4 D3 D2 D1 D0
X X X X CLKINV CLKPHASE1 CLKPHASE0 DCS
Bits 7-4 Unused Bit
Bit 3 CLKINV Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1 CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
01 = CLKOUT
+
/CLKOUT
–
delayed by 45° (Clock Period • 1/8)
10 = CLKOUT
+
/CLKOUT
–
delayed by 90° (Clock Period • 1/4)
11 = CLKOUT
+
/CLKOUT
–
delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0 DCS Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On