Datasheet

17
215814f
LTC2158-14
Figure 12. Functional Equivalent of Digital Output Randomizer
Figure 13. Decoding a Randomized Digital
Output Signal
applicaTions inForMaTion
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
A
IN
+
– A
IN
–
(1.32V Range) OF
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>0.66V
+0.66V
+0.6599194V
1
0
0
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
+0.0000806V
+0.000000V
–0.0000806V
–0.0001611V
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–0.6599194V
–0.66V
< –0.66V
0
0
1
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The LSB, OF and CLKOUT out-
puts are not affected. The output randomizer is enabled
by serially programming mode control register A4.
CLKOUT CLKOUT
OF
D13/D0
D12/D0
•
•
•
D1/D0
D0
215814 F12
OF
D13
D12
D1
D0
RANDOMIZER
ON
D13
FPGA
PC BOARD
D12
•
•
•
D1
D0
215814 F13
D0
D1/D0
D12/D0
D13/D0
OF
CLKOUT
LTC2158-14