Datasheet

15
215814f
LTC2158-14
applicaTions inForMaTion
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. The duty cycle
stabilizer is enabled via SPI Register A2 (see Table 3) or
by CS in parallel programming mode.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. In
this case, care should be taken to make the clock a 50%
(±5%) duty cycle.
DIGITAL OUTPUTS
The digital outputs are double data rate LVDS signals. Two
data bits are multiplexed and output on each differential
Figure 9. Sinusoidal Encode Drive
output pair. There are seven LVDS output pairs for channel
A (DA0_1
+
/DA0_1
–
through DA12_13
–
/DA12_13
+
) and
seven pairs for channel B (DB0_1
+
/DB0_1
–
through
DB12_13
–
/DB12_13
+
). Overflow (OF
+
/OF
–
) and the data
output clock (CLKOUT
+
/CLKOUT
–
) each have an LVDS
output pair. Note that overflow for both channels is mul-
tiplexed onto the OF
+
/OF
–
output pair.
By default the outputs are standard LVDS levels: 3.5
mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OV
DD
and OGND which are
isolated from the A/D core power and ground.
LTC2158-14
V
DD
215814 F09
1.2V
10k
50Ω
100Ω
50Ω
0.1µF
0.1µF
T1: MACOM
ETC1-1-13
Figure 10. PECL or LVDS Encode Drive
V
DD
LTC2158-14
PECL OR
LVDS INPUT
215814 F10
1.2V
10k
100Ω
0.1µF
0.1µF
ENC
+
ENC
–