Datasheet

21
21576512f
LTC2157-12/
LTC2156-12/LTC2155-12
Figure 12. Functional Equivalent of Digital Output Randomizer
Figure 13. Decoding a Randomized Digital
Output Signal
APPLICATIONS INFORMATION
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
A
IN
+
– A
IN
–
(1.5V Range) OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>0.75 V
+0.75V
+0.7496337V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
+0.0003662V
+0.000000V
–0.0003662V
–0.0007324V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.74963378V
–0.75V
< –0.75V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is randomized by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The LSB, OF and CLKOUT out-
puts are not affected. The output randomizer is enabled
by serially programming mode control register A4.
CLKOUT CLKOUT
OF
D11/D0
D10/D0
•
•
•
D1/D0
D0
21576512 F12
OF
D11
D10
D1
D0
RANDOMIZER
ON
D11
FPGA
PC BOARD
D10
•
•
•
D1
D0
21576512 F13
D0
D1/D0
D10/D0
D11/D0
OF
CLKOUT
LTC2157-12